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公开(公告)号：US11606186B2
公开(公告)日：2023-03-14
申请号：US17684273
申请日：2022-03-01
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
摘要： Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
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公开(公告)号：US20230010756A1
公开(公告)日：2023-01-12
申请号：US17813533
申请日：2022-07-19
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
IPC分类号： G06F1/3296 , G01R31/30 , G05F1/46 , G06F1/324 , H04L25/02
摘要： Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.
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公开(公告)号：US20220329467A1
公开(公告)日：2022-10-13
申请号：US17851740
申请日：2022-06-28
申请人： Kandou Labs, S.A.
发明人： John Fox , Brian Holden , Ali Hormati , Peter Hunt , John D. Keay , Amin Shokrollahi , Richard Simpson , Anant Singh , Andrew Kevin John Stewart , Giuseppe Surace , Roger Ulrich
IPC分类号： H04L25/08 , H04L25/14 , H04L25/02 , H04L25/03 , H04L25/49 , H04L5/02 , H04L27/01 , H01Q13/24 , H01L29/768 , H01Q13/28 , G01R31/3183 , H01R12/00
摘要： A pair of ground planes arranged in parallel, a dielectric medium disposed in between the pair of ground planes, and a set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors having (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code.
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公开(公告)号：US20220311649A1
公开(公告)日：2022-09-29
申请号：US17590450
申请日：2022-02-01
申请人： Kandou Labs, S.A.
发明人： Amin Shokrollahi
摘要： Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.
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公开(公告)号：US20220191073A1
公开(公告)日：2022-06-16
申请号：US17684268
申请日：2022-03-01
申请人： Kandou Labs, S.A.
发明人： Ali Hormati
摘要： Methods and systems are described for generating a time-varying information signal at an output of a variable gain amplifier (VGA), sampling, using a sampler having a vertical decision threshold associated with a target signal amplitude, the time-varying information signal asynchronously to generate a sequence of decisions from varying sampling instants in sequential signaling intervals, the sequence of decisions comprising (i) positive decisions indicating the time-varying information signal is above the target signal amplitude and (ii) negative decisions indicating the time-varying information signal is below the target signal amplitude, accumulating a ratio of positive decisions to negative decisions, and generating a gain feedback control signal to adjust a gain setting of the VGA responsive to a mismatch of the accumulated ratio with respect to a target ratio.
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公开(公告)号：US11018675B2
公开(公告)日：2021-05-25
申请号：US16566648
申请日：2019-09-10
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
IPC分类号： H03L7/08 , H03L7/087 , H03L7/099 , H04L7/033 , H04L25/14 , H04L25/02 , H04L25/40 , H04L25/493 , H03K19/21 , H03L7/089 , H04L7/00
摘要： Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.
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公开(公告)号：US10983587B2
公开(公告)日：2021-04-20
申请号：US16218386
申请日：2018-12-12
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
摘要： Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.
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公开(公告)号：US10931249B2
公开(公告)日：2021-02-23
申请号：US16378461
申请日：2019-04-08
申请人： Kandou Labs, S.A.
发明人： Suhas Rattan , Kiarash Gharibdoust
摘要： The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.
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公开(公告)号：US10819541B2
公开(公告)日：2020-10-27
申请号：US16836551
申请日：2020-03-31
申请人： Kandou Labs SA
发明人： Ali Hormati , Armin Tajalli , Amin Shokrollahi
摘要： Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.
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100.发明授权公开(公告)号：US10812298B2
公开(公告)日：2020-10-20
申请号：US16444951
申请日：2019-06-18
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
摘要： Pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising a set of data signal nodes and a set of DFE correction nodes, in response to a sampling clock, generating a differential data voltage and an aggregate differential DFE correction signal, and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock.
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