公开(公告)号：US20190172826A1

公开(公告)日：2019-06-06

申请号：US16252825

申请日：2019-01-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/06 ,  H01L23/522

Abstract: A 3D semiconductor wafer, the wafer including: a first device, where the first device includes a first level, the first level including first transistors, and where the first device includes a second level, the second level including first interconnections; a second device overlaying the first device, where the second device includes a third level, the third level including second transistors, and where the second device includes a fourth level, the fourth level including second interconnections, where the first device is substantially larger in area than the second device; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors.

公开(公告)号：US20190148234A1

公开(公告)日：2019-05-16

申请号：US16228757

申请日：2018-12-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L21/8238 ,  G11C17/14 ,  H01L21/683 ,  H01L29/786 ,  H01L29/78 ,  H01L21/84 ,  G11C29/00 ,  G11C17/06 ,  G11C16/04 ,  H03K19/177 ,  H03K19/0948 ,  H03K17/687 ,  H01L27/118 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L25/18 ,  H01L21/762 ,  H01L25/065 ,  H01L23/544 ,  H01L23/525 ,  H01L23/36

Abstract: A method for producing a 3D memory device including: providing a first level including a single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; performing additional processing steps to form memory cells within the second level and within the third level, each of the first memory cells include one first transistor, each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having the same doping type, the memory is NAND, the first level includes memory peripheral circuits, at least one of the first memory cells is at least partially atop a portion of the peripheral circuits.

公开(公告)号：US10290682B2

公开(公告)日：2019-05-14

申请号：US15803732

申请日：2017-11-03

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L29/06 ,  H01L47/00 ,  H01L27/24 ,  H01L27/108 ,  H01L29/78 ,  H01L27/12 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/11 ,  H01L27/06 ,  H01L21/84 ,  H01L21/822 ,  H01L21/762 ,  H01L21/683 ,  H01L21/268 ,  H01L27/22 ,  H01L29/423 ,  H01L45/00 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/105

Abstract: A 3D semiconductor device, the device including: first transistors; second transistors, overlaying the first transistors; third transistors, overlaying the second transistors; and fourth transistors, overlaying the third transistors, where the second transistors, the third transistors and the fourth transistors are self-aligned, being processed following the same lithography step, and where at least one of the first transistors is part of a control circuit controlling at least one of the second transistors, at least one of the third transistors and at least one of the fourth transistors.

公开(公告)号：US20190123188A1

公开(公告)日：2019-04-25

申请号：US16226628

申请日：2018-12-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L29/78 ,  H01L27/115 ,  G11C11/404 ,  H01L27/11 ,  H01L27/24 ,  G11C11/4097 ,  G11C16/02 ,  H01L27/108 ,  H01L27/11578

Abstract: A 3D semiconductor device including: a first level including a single crystal layer, a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the single crystal layer and includes interconnects between the first transistors forming control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; and polysilicon pillars, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the third transistors, where at least one of the second memory cells is at least partially atop of the control circuits.

公开(公告)号：US20190074371A1

公开(公告)日：2019-03-07

申请号：US16174152

申请日：2018-10-29

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L29/78

Abstract: A 3D semiconductor device, the device including: a first layer including first transistors each including a first silicon channel; a second layer including second transistors each including a second silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer overlying the second transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistors are junction-less transistors.

公开(公告)号：US10224279B2

公开(公告)日：2019-03-05

申请号：US14814865

申请日：2015-07-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/528 ,  H01L27/108 ,  G11C8/16 ,  H01L27/06 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  G11C5/02 ,  G11C5/04 ,  G11C11/403

Abstract: A 3D device, including: a first layer including a first memory including a first transistor; a second layer including a second memory including a second transistor; and a Resistive RAM structure, where the second transistor is self-aligned to the first transistor, and where the Resistive RAM structure is overlaying the first layer and is overlaid by the second layer.

公开(公告)号：US10217667B2

公开(公告)日：2019-02-26

申请号：US15904347

申请日：2018-02-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L21/822 ,  H01L25/065 ,  H01L21/683 ,  H01L29/786 ,  H01L29/78 ,  H01L21/84 ,  G11C29/00 ,  G11C17/06 ,  G11C16/04 ,  H03K19/177 ,  H03K19/0948 ,  H03K17/687 ,  H01L27/118 ,  H01L27/112 ,  H01L27/108 ,  H01L27/105 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L25/18 ,  H01L21/762 ,  H01L23/544 ,  H01L23/525 ,  H01L23/36 ,  G11C17/14 ,  H01L21/8238 ,  H01L27/11 ,  H01L23/00 ,  H01L23/48

Abstract: A 3D memory device, the device including: a first single crystal layer including memory peripheral circuits; a first memory layer including a first junction-less transistor; a second memory layer including a second junction-less transistor; and a third memory layer including a third junction-less transistor, where the first memory layer overlays the first single crystal layer, where the second memory layer overlays the first memory layer, where the third memory layer overlays the second memory layer, where the first junction-less transistor, the second junction-less transistor and the third junction-less transistor are formed by a single lithography and etch process, and where the first memory layer includes a nonvolatile NAND type memory.

公开(公告)号：US20190006222A1

公开(公告)日：2019-01-03

申请号：US16101489

申请日：2018-08-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L21/683 ,  H01L29/792 ,  G11C8/16 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12 ,  H01L27/118 ,  H01L27/11578 ,  H01L27/11573 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/11526 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/10 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L23/525 ,  H01L23/48 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/768 ,  H01L21/762 ,  H01L21/74 ,  H01L29/788 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367

Abstract: A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.

公开(公告)号：US20180277530A1

公开(公告)日：2018-09-27

申请号：US15990626

申请日：2018-05-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/00 ,  H01L21/304 ,  H01L25/18 ,  H01L21/78

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/76243 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/7806 ,  H01L25/18

Abstract: A method for processing a 3D semiconductor device, the method including: providing a wafer including a plurality of first dies, the plurality of first dies including a first transistor layer and a first interconnection layer; completing a step of transferring a plurality of second dies each overlaying at least one of the first dies, where each of the plurality of second dies includes a second transistor layer, where at least one of the plurality of first dies is substantially larger in area than at least one of the plurality of second dies, and where each of the plurality of second dies has a thickness greater than six microns; and completing a step of thinning the plurality of second dies, where each of the plurality of second dies has a thickness of less than 2 microns.

公开(公告)号：US10043781B2

公开(公告)日：2018-08-07

申请号：US15904377

申请日：2018-02-25

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/367 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; at least one connection from the plurality of first transistors to a plurality of through silicon vias (TSVs); a plurality of third transistors overlaying the plurality of second transistors, where the plurality of second transistors are self-aligned to the plurality of third transistors having been processed following the same lithography step; and a first memory array and a second memory array, where the first memory array includes the plurality of second transistors and the second memory array includes the plurality of third transistors.