公开(公告)号：US09715269B2

公开(公告)日：2017-07-25

申请号：US14583333

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Seh W. Kwa ,  Neil Songer ,  Rob Gough ,  David J. Harriman

IPC: G06F1/00 ,  G06F1/32 ,  G06F13/42 ,  G06F13/24

CPC classification number: G06F1/324 ,  G06F1/3209 ,  G06F13/24 ,  G06F13/4221 ,  G06F13/4265 ,  Y02B60/1235 ,  Y02D10/151

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

公开(公告)号：US20170206083A1

公开(公告)日：2017-07-20

申请号：US15475680

申请日：2017-03-31

Applicant: HONG WANG ,  PER HAMMARLUND ,  XIANG ZOU ,  JOHN P. SHEN ,  XINMIN TIAN ,  MILIND GIRKAR ,  PERRY H. WANG ,  PIYUSH N. DESAI

Inventor： HONG WANG ,  PER HAMMARLUND ,  XIANG ZOU ,  JOHN P. SHEN ,  XINMIN TIAN ,  MILIND GIRKAR ,  PERRY H. WANG ,  PIYUSH N. DESAI

IPC: G06F9/30 ,  G06F12/0875 ,  G06F11/30 ,  G06F9/48 ,  G06F11/34

CPC classification number: G06F13/24 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  G06F11/3024 ,  G06F11/348 ,  G06F12/0875 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/452

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

公开(公告)号：US09710409B2

公开(公告)日：2017-07-18

申请号：US14267982

申请日：2014-05-02

Applicant: FUJITSU LIMITED

Inventor： Takehiko Murata

IPC: G06F13/24 ,  G06F9/54

CPC classification number: G06F13/24 ,  G06F9/54

Abstract: PCI devices write an MSI message in a memory and polling routines, which are executed by CPU cores respectively, poll the memory. The polling routines poll a cause of interrupt during an interval between tasks, during an interval between threads, and during idle and cause a CPU core with the lowest load to perform interrupt processing. An IO task performs inter-task communication with another IO task by using a command queue.

公开(公告)号：US09703747B2

公开(公告)日：2017-07-11

申请号：US14283751

申请日：2014-05-21

Applicant: DELL PRODUCTS L.P.

Inventor： Vivek Dharmadhikari ,  Vinay Sawal ,  Shree Murthy ,  Timothy Thinh Mai

IPC: G06F13/24 ,  G06F13/42 ,  H04L12/24

CPC classification number: G06F13/4221 ,  G06F13/24 ,  H04L41/0836

Abstract: Embodiments of the present invention facilitate access to an information handling system, such as a port extender, from a remote information handling device, such as a controlling bridge. According to embodiments of the invention, a port extender, responsive to receiving a request from a controlling bridge for console access to the port extender, submits one or more instructions to a MUX to switch control of a UART from a host CPU of the port extender to a protocol extension message processor residing on the port extender, and switches control by the MUX of the UART to the processor according to the one or more instructions.

公开(公告)号：US20170192915A1

公开(公告)日：2017-07-06

申请号：US15464892

申请日：2017-03-21

Applicant: ARM Limited

Inventor： Michael Alexander KENNEDY ,  Anthony JEBSON

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F9/4812 ,  G06F9/5027

Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.

公开(公告)号：US20170192450A1

公开(公告)日：2017-07-06

申请号：US15159958

申请日：2016-05-20

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin-Ho ON

IPC: G06F1/08 ,  G06F9/50 ,  G06F9/48 ,  G06F13/24

CPC classification number: G06F1/08 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/4825 ,  G06F9/505 ,  G06F13/24

Abstract: An apparatus and method for performing the dynamic frequency control of a central processing unit (CPU). The apparatus for performing the dynamic frequency control of a central processing unit (CPU) includes a frequency setting unit, a latency measurement unit, a frequency adjustment unit, and a control unit. The frequency setting unit sets optimum frequency using the measured amount of load. The latency measurement unit measures scheduler execution information. The frequency adjustment unit adjusts the optimum frequency using the scheduler execution information. The control unit incorporates the adjusted optimum frequency into a CPU.

公开(公告)号：US09698786B2

公开(公告)日：2017-07-04

申请号：US14725366

申请日：2015-05-29

Applicant: Nexperia B.V.

Inventor： Madan Mohan Reddy Vemula ,  Harold Hanson

IPC: H03K17/30 ,  G06F13/20 ,  H03K19/0185 ,  G06F13/24 ,  G06F13/40

CPC classification number: H03K19/0185 ,  G06F13/24 ,  G06F13/4068 ,  H03K2217/0054

Abstract: Aspects of the present disclosure are directed to detecting and powering external circuits via a common port. As may be implemented in accordance with one or more embodiments, an accessory detection circuit detects a type of an external circuit based upon a pull-down resistance at an interface port (e.g., where each accessory type provides a discernable pull-down resistance). Power switching circuitry couples power between the interface port and an internal power-based circuit, and operates in an open condition when the accessory detection circuit is active. An adaptive biasing circuit sets a voltage across the power switching circuitry to about zero, based on a voltage level provided on the interface port, thereby mitigating changes in the pull-down resistance due to current leakage. Once the type of external circuit is identified, the power switching circuitry couples power between the external circuit and the internal circuit.

公开(公告)号：US09697354B2

公开(公告)日：2017-07-04

申请号：US14696159

申请日：2015-04-24

Applicant: Dell Products L.P.

Inventor： Allen Wynn

IPC: G06F3/00 ,  G06F13/24 ,  G06F13/00 ,  G06F13/28 ,  H04L29/06 ,  G06F21/54 ,  G06F21/46 ,  G06F1/32

CPC classification number: G06F13/24 ,  G06F1/3275 ,  G06F21/46 ,  G06F21/54 ,  Y02D10/14

Abstract: In accordance with the present disclosure, a system and method are herein disclosed for providing secure SMI memory services, including the protection of SMM memory from surreptitious attacks by, for example, rootkits. Information handling systems are susceptible to attacks, especially attacks on SMM memory. In one example, an SMI handler corresponding to the SMI Driver associated with an SMI interrupt performs validation of a password. An SSMS driver allocates memory for the SMI handler to use with the validation process and also performs a secure erase of allocated memory blocks upon completion of all secure SMI Memory Services. By controlling the validation and secure erase process through the use of the SMI handler and SSMS driver, information leakage can be prevented resulting in system data integrity.

公开(公告)号：US20170185320A1

公开(公告)日：2017-06-29

申请号：US15313736

申请日：2014-07-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Michael R. Krause

IPC: G06F3/06 ,  G06F13/24

CPC classification number: G06F3/0613 ,  G06F3/0655 ,  G06F3/068 ,  G06F13/24

Abstract: A requester sends, to a responding component, a request to cause the responding component to perform a computation. The requester sends, to the responding component, a delayed read indication, where the delayed read indication indicates that a result of the computation is not to be returned to the requester from the responding component until a data value at a target address of the delayed read indication has changed. The requester receives, from the responding component, an acknowledgment of the delayed read indication, and after receiving the acknowledgment, receives a response to the request without the requester sending another request to the responding component.

公开(公告)号：US09684613B2

公开(公告)日：2017-06-20

申请号：US14277920

申请日：2014-05-15

Applicant: Seagate Technology LLC

Inventor： Nital Patwa ,  Timothy Canepa ,  Yimin Chen

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F2213/2408 ,  Y02D10/14

Abstract: A storage controller of a data storage system maintains, for each interrupt vector, (1) a pending status that indicates whether one or more completions are pending in the completion queue (CQ) associated with the interrupt vector, and (2) an in-progress status that indicates whether or not the storage controller is currently in the process of composing an interrupt. The storage controller utilizes these two statuses to reduce or eliminate spurious interrupts by preventing an interrupt from being composed if there are no completions in the CQ, by preventing an interrupt from being composed if the corresponding interrupt mask has been set before composition of the interrupt begins, and by preventing an interrupt from being sent to the host system in cases where the interrupt mask was set after composition of the interrupt began, but before the interrupt has been sent to the host system.