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公开(公告)号：US20200091398A1
公开(公告)日：2020-03-19
申请号：US16576432
申请日：2019-09-19
申请人： Ambature, Inc.
摘要： According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers.
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公开(公告)号：US10592814B2
公开(公告)日：2020-03-17
申请号：US15828613
申请日：2017-12-01
摘要： Generating a layout for a multi-qubit chip is provided. A schematic is received as input. The schematic input includes a plurality of qubits, a plurality of coupling busses, a bus design parameter specifying a bus frequency, a plurality of readout busses, and a plurality of readout ports. A qubit design is selected from a qubit library, based on the qubit style in the schematic input. A bus style is selected from a bus information library, based on the bus style in the schematic input. A qubit layout is automatically generated by assembling the selected bus style/, selected qubit design, the plurality of readout busses and the plurality of readout ports.
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公开(公告)号：US20200052181A1
公开(公告)日：2020-02-13
申请号：US16597604
申请日：2019-10-09
IPC分类号： H01L39/02 , G06N10/00 , H01L21/3205 , H01L21/768 , H01L23/48 , H01L23/532 , H01L39/22 , H01L39/24 , H03K19/195 , H01L27/18
摘要： A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.
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公开(公告)号：US20200043977A1
公开(公告)日：2020-02-06
申请号：US16054326
申请日：2018-08-03
摘要： Symmetrical qubits with reduced far-field radiation are provided. In one example, a qubit device includes a first group of superconducting capacitor pads positioned about a defined location of the qubit device, wherein the first group of superconducting capacitor pads comprise two or more superconducting capacitor pads having a first polarity, and a second group of superconducting capacitor pads positioned about the defined location of the qubit device in an alternating arrangement with the first group of superconducting capacitor pads, wherein the second group of superconducting capacitor pads comprise two or more superconducting capacitor pads having a second polarity that is opposite the first polarity.
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公开(公告)号：US20200036330A1
公开(公告)日：2020-01-30
申请号：US16048935
申请日：2018-07-30
发明人： Baleegh Abdo
摘要： A superconducting device that mixes surface acoustic waves and techniques for fabricating the same are provided. A superconducting device can comprise a first surface acoustic wave resonator comprising a first low-loss piezo-electric dielectric substrate. The superconducting device can also comprise a second surface acoustic wave resonator comprising a second low-loss piezo-electric dielectric substrate. Further, the superconducting device can comprise a Josephson ring modulator coupled to the first surface acoustic wave resonator and the second surface acoustic wave resonator. The Josephson ring modulator is a dispersive nonlinear three-wave mixing element.
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公开(公告)号：US20200035902A1
公开(公告)日：2020-01-30
申请号：US16047192
申请日：2018-07-27
摘要： Techniques for a quantum device with modular quantum building blocks are provided. In one embodiment, a device is provided that comprises a substrate that is coupled with a plurality of qubit pockets, where at least one qubit pocket of the plurality of qubit pockets is coupled with a qubit. In one implementation, the device can further comprise a plurality of connectors coupled to the substrate and positioned around at least a portion of the substrate, where the plurality of connectors comprising a connecting element. In one or more implementations, the device can further comprise a plurality of transmission lines formed on the substrate and connect at least one connector of the plurality of connectors to at least one qubit pocket of the plurality of qubit pockets.
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公开(公告)号：US20200035901A1
公开(公告)日：2020-01-30
申请号：US16047516
申请日：2018-07-27
摘要： Techniques for implementing multiple microwave attenuators on a high thermal conductivity substrate for cryogenic applications to reduce heat and thermal noise during quantum computing are provided. In one embodiment, a device for using in cryogenic environment is provided that comprises a substrate having a thermal conductivity above a defined threshold, a plurality of transmission lines fabricated on the substrate and arranged with a separation gap between the plurality of transmission lines to maintain crosstalk below −50 decibels, and one or more microwave attenuators embedded on the plurality of transmission lines.
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公开(公告)号：US10546993B2
公开(公告)日：2020-01-28
申请号：US16037539
申请日：2018-07-17
IPC分类号： H03K19/195 , H01L39/02 , G06N10/00
摘要： Systems and methods are provided for a ZZZ coupler. A first tunable coupler is coupled to the first qubit and tunable via a first control signal. A second tunable coupler is coupled to the first tunable coupler to direct a flux of the first qubit into a tuning loop of the second tunable coupler, such that when a first coupling strength associated with the first tunable coupler is non-zero, a second coupling strength, associated with the second tunable coupler, is a function of a second control signal applied to the second tunable coupler and a state of the first qubit. The second qubit and the third qubit are coupled to one another through the second tunable coupler, such that, when the second coupling strength is non-zero it is energetically favorable for the states of the first and second qubits to assume a specific relationship with respect to the Z-axis.
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公开(公告)号：US10546621B2
公开(公告)日：2020-01-28
申请号：US16013549
申请日：2018-06-20
摘要： Magnetic Josephson junction driven flux-biased superconductor memory cell and methods are provided. A memory cell may include a magnetic Josephson junction (MJJ) superconducting quantum interference device (SQUID) comprising a first MJJ device and a second MJJ device, arranged in parallel to each other, where the MJJ SQUID is configured to generate a first flux-bias or a second flux-bias, where the first flux-bias corresponds to a first direction of current flow in the MJJ SQUID and the second flux-bias corresponds to a second direction of current flow in the MJJ SQUID. The memory cell may further include a superconducting metal-based superconducting quantum interference device (SQUID) including a first Josephson junction (JJ) and a second JJ, arranged in parallel to each other, where each of the first JJ and the second JJ has a critical current responsive to any flux-bias generated by the MJJ SQUID.
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100.发明申请公开(公告)号：US20200028064A1
公开(公告)日：2020-01-23
申请号：US16417711
申请日：2019-05-21
摘要： A technique relates to a trilayer Josephson junction structure. A dielectric layer is on a base electrode layer that is on a substrate. A counter electrode layer is on the dielectric layer. First and second counter electrodes are formed from the counter electrode layer. First and second dielectric layers are formed from the dielectric layer. First and second base electrodes are formed from base electrode layer. The first counter electrode, first dielectric layer, and first base electrode form a first stack. The second counter electrode, second dielectric layer, and second base electrode form a second stack. A shunting capacitor is between first and second base electrodes. An ILD layer is deposited on the substrate, the first and second counter electrodes, and the first and second base electrodes. A contact bridge connects the first and second counter electrodes. An air gap is formed underneath the contact bridge by removing ILD.
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