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公开(公告)号：US11700777B2
公开(公告)日：2023-07-11
申请号：US17021585
申请日：2020-09-15
IPC分类号： H01L29/66 , H10N69/00 , H10N60/01 , G01R33/035 , H03K19/195 , H10N60/12 , H10N60/80
CPC分类号： H10N69/00 , H10N60/0912 , G01R33/0354 , H03K19/195 , H10N60/12 , H10N60/805
摘要： Techniques related to vertical silicon-on-metal superconducting quantum interference devices and method of fabricating the same are provided. Also provided are associated flux control and biasing circuitry. A superconductor structure can comprise a silicon-on-metal substrate that can comprise a first superconducting layer, comprising a first superconducting material, between a first crystalline silicon layer and a second crystalline silicon layer. The superconducting structure can also comprise a first via comprising a first Josephson junction and a second via comprising a second Josephson junction. The first via and the second via can be formed between the first superconducting layer and a second superconducting layer, comprising a second superconducting material. An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.
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公开(公告)号：US11538854B2
公开(公告)日：2022-12-27
申请号：US16833479
申请日：2020-03-27
发明人： Firat Solgun , Dongbing Shao , Markus Brink
摘要： A system includes a first quantum circuit plane that includes a first qubit, a second qubit and a third qubit. A coupled-line bus is coupled between the first qubit and the second qubit. A second circuit plane is connected to the first quantum circuit plane, comprising a control line coupled to the third qubit. The control line and the coupled-line bus are on different planes and crossing over each other, and configured to mitigate cross-talk caused by the crossing during signal transmission.
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3.发明授权公开(公告)号：US11527697B2
公开(公告)日：2022-12-13
申请号：US17110836
申请日：2020-12-03
摘要： A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.
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公开(公告)号：US11501196B2
公开(公告)日：2022-11-15
申请号：US16200062
申请日：2018-11-26
发明人： Albert Frisch , Harry Barowski , Markus Brink
摘要： An embodiment of a qubit tuning device includes a first layer configured to generate a magnetic field, the first layer comprising a material exhibiting superconductivity in a cryogenic temperature range. In an embodiment, the qubit tuning device includes a qubit of a quantum processor chip, wherein the first layer is configured to magnetically interact with the qubit such that a first magnetic flux of the first layer causes a first change in a first resonance frequency of the qubit by a first frequency shift value.
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5.发明申请公开(公告)号：US20220232710A1
公开(公告)日：2022-07-21
申请号：US17658283
申请日：2022-04-07
发明人： Baleegh Abdo , Markus Brink
摘要： Fabrication of superconducting devices that combine or separate direct currents and microwave signals is provided. A method can comprise forming a direct current circuit that supports a direct current, a microwave circuit that supports a microwave signal, and a common circuit that supports the direct current and the microwave signal. The method can also comprise operatively coupling a first end of the direct current circuit and a first end of the microwave circuit to a first end of the common circuit. The direct current circuit can comprise a bandstop circuit and the microwave circuit can comprise a capacitor. Alternatively, the direct current circuit can comprise a bandstop circuit and the microwave circuit can comprise a bandpass circuit. Alternatively, the microwave circuit can comprise a capacitor and the direct current circuit can comprise one or more quarter-wavelength transmission lines.
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公开(公告)号：US11205035B1
公开(公告)日：2021-12-21
申请号：US16909542
申请日：2020-06-23
发明人： Dongbing Shao , Markus Brink
IPC分类号： G06F30/30 , H01L23/00 , G06F30/398 , G06F30/39 , G06F30/392 , G06F30/337 , G06F30/327 , G06F111/12 , G06F111/14 , G06F30/394 , G06F30/3308 , B82Y10/00 , G06N10/00 , G06F113/18 , G06F115/12 , H01L23/498
摘要： Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.
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公开(公告)号：US20210305315A1
公开(公告)日：2021-09-30
申请号：US16833479
申请日：2020-03-27
发明人： Firat Solgun , Dongbing Shao , Markus Brink
摘要： A system includes a first quantum circuit plane that includes a first qubit, a second qubit and a third qubit. A coupled-line bus is coupled between the first qubit and the second qubit. A second circuit plane is connected to the first quantum circuit plane, comprising a control line coupled to the third qubit. The control line and the coupled-line bus are on different planes and crossing over each other, and configured to mitigate cross-talk caused by the crossing during signal transmission.
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8.发明申请公开(公告)号：US20210183793A1
公开(公告)日：2021-06-17
申请号：US16711064
申请日：2019-12-11
IPC分类号： H01L23/64 , H01L27/18 , H01L23/498 , G06N10/00
摘要： According to an embodiment of the present invention, a quantum processor includes a qubit chip. The qubit chip includes a substrate, and a plurality of qubits formed on a first surface of the substrate. The plurality of qubits are arranged in a pattern, wherein nearest-neighbor qubits in the pattern are connected. The quantum processor also includes a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, wherein the first and second qubits are separated by at least a third qubit in the pattern.
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公开(公告)号：US11038093B2
公开(公告)日：2021-06-15
申请号：US16943572
申请日：2020-07-30
发明人： Dongbing Shao , Markus Brink
摘要： A configuration of wirebonds for reducing cross-talk in a quantum computing chip includes a first wirebond coupling a first conductor of a quantum computing circuit with a first conductor of an external circuit. The embodiment further includes in the configuration a second wirebond coupling a second conductor of the quantum computing circuit with a second conductor of the external circuit, wherein the first wirebond and the second wirebond are separated by a first vertical distance in a direction of a length of the first conductor.
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公开(公告)号：US10784432B2
公开(公告)日：2020-09-22
申请号：US16246676
申请日：2019-01-14
IPC分类号： H01L39/22 , H01L39/24 , H03K19/195 , H01L39/12 , B82Y10/00 , H01L27/18 , H01L39/02 , B82Y40/00 , G06N10/00
摘要： Techniques for a vertical Josephson junction superconducting device are provided. In one embodiment, a chip surface base device structure is provided that comprises a substrate comprising crystalline silicon that is coupled with a first superconducting layer, wherein the first superconducting layer is coupled with a second substrate comprising crystalline silicon. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in an etched region of the substrate, the vertical Josephson junction comprising a first superconducting layer, a tunnel barrier layer, and a top superconducting layer.
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