公开(公告)号：US12039402B2

公开(公告)日：2024-07-16

申请号：US16998851

申请日：2020-08-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jared Barney Hertzberg ,  Alan E. Rosenbluth ,  Dongbing Shao

IPC: G06N10/00

CPC classification number: G06N10/00

Abstract: A method of frequency allocation in a quantum device having a plurality of qubits includes determining a plurality of frequency groups based on a configuration of the plurality of qubits; determining, for each of the plurality of qubits, a qubit frequency; assigning a frequency group from the plurality of frequency groups to each of the plurality of qubits based on each respective qubit frequency; determining for at least one qubit of the plurality of qubits whether a frequency collision exists between the at least one qubit and neighboring qubits in the plurality of qubits based on the qubit frequency of the at least one qubit and at least one qubit frequency of the neighboring qubits; and adjusting the frequency of the at least one qubit based on the determination whether a frequency collision exists between the at least one qubit and said neighboring qubits in the plurality of qubits. A non-transitory computer-readable medium for frequency allocation in a quantum device includes instructions to perform the method.

公开(公告)号：US20220181154A1

公开(公告)日：2022-06-09

申请号：US17677469

申请日：2022-02-22

Applicant: International Business Machines Corporation

Inventor： Rasit Onur Topaloglu ,  Kafai Lai ,  Dongbing Shao ,  Zheng Xu

IPC: H01L21/033 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

公开(公告)号：US20210240899A1

公开(公告)日：2021-08-05

申请号：US16779179

申请日：2020-01-31

Applicant: International Business Machines Corporation

Inventor： Dongbing Shao ,  Rasit Onur Topaloglu ,  Geng Han ,  Yuping Cui

IPC: G06F30/392 ,  G06F30/398

Abstract: Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.

公开(公告)号：US10915690B2

公开(公告)日：2021-02-09

申请号：US16383326

申请日：2019-04-12

Applicant: International Business Machines Corporation

Inventor： Dongbing Shao ,  Yongan Xu ,  Shyng-Tsong Chen ,  Zheng Xu

IPC: G06F30/30 ,  G06F30/398

Abstract: Methods and systems for performing an electronic design. A layout of a via of an electronic design is obtained and a determination is made if the layout of the via satisfies one or more retargeting conditions, at least one of the retargeting conditions being that a first edge of a metal line is within a specified distance from a first edge of the via and a second edge of the metal line is within the specified distance from a second edge of the via, the first edge of the metal line being parallel to the first edge of the via and the second edge of the metal line being parallel to the second edge of the via; and reducing a resistance of the via by the layout of the via is retargeted in response to the retargeting conditions being satisfied.

公开(公告)号：US10903412B2

公开(公告)日：2021-01-26

申请号：US16389001

申请日：2019-04-19

Applicant: International Business Machines Corporation

Inventor： Dongbing Shao ,  Markus Brink ,  Firat Solgun ,  Jared Barney Hertzberg

IPC: H01L39/22 ,  H01L39/24 ,  G06N10/00

Abstract: A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

公开(公告)号：US10790271B2

公开(公告)日：2020-09-29

申请号：US15954819

申请日：2018-04-17

Applicant: International Business Machines Corporation

Inventor： Zheng Xu ,  Chen Zhang ,  Ruqiang Bao ,  Dongbing Shao

IPC: H01L21/84 ,  H01L25/00 ,  H01L21/762 ,  H01L25/07 ,  H01L23/00 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes forming a first field-effect transistor (FET) on a substrate, the first FET comprising a first plurality of channel regions extending in a first direction, and stacking a second FET on the first FET, the second FET comprising a second plurality of channel regions extending in a second direction perpendicular to the first direction, wherein the first FET comprises a first gate region extending in the second direction across the first plurality of channel regions, and the second FET comprises a second gate region extending in the first direction across the second plurality of channel regions.

公开(公告)号：US20200125695A1

公开(公告)日：2020-04-23

申请号：US16166892

申请日：2018-10-22

Applicant: International Business Machines Corporation

Inventor： Dongbing Shao ,  Jing Sha ,  Kafai Lai

IPC: G06F17/50 ,  G06N3/04 ,  G06K9/32 ,  G06K9/62

Abstract: A method for detecting hotspots in physical design layout patterns includes receiving a given physical design layout pattern, utilizing a hotspot detection model to detect one or more potential hotspots in the given physical design layout pattern, and performing verification to determine whether a given one of the potential hotspots detected by the hotspot detection model comprises a real hotspot or a nonexistent hotspot. The method also includes, responsive to determining that the given potential hotspot comprises an actual hotspot, modifying the given physical design layout pattern to remove the actual hotspot. The method further includes, responsive to determining that the given potential hotspot comprises a nonexistent hotspot, augmenting the hotspot detection model with additional training data generated based on the nonexistent hotspot.

公开(公告)号：US20200082048A1

公开(公告)日：2020-03-12

申请号：US16682365

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dongbing Shao ,  Zheng Xu ,  Lawrence A. Clevenger

IPC: G06F17/50

Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.

公开(公告)号：US20200082047A1

公开(公告)日：2020-03-12

申请号：US16682304

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dongbing Shao ,  Zheng Xu ,  Lawrence A. Clevenger

IPC: G06F17/50

Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.

公开(公告)号：US10585346B2

公开(公告)日：2020-03-10

申请号：US15819213

申请日：2017-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Chieh-Yu Lin ,  Dongbing Shao ,  Kehan Tian ,  Zheng Xu

IPC: G06F17/50 ,  G03F1/36 ,  G03F1/70 ,  G03F1/38

Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.