公开(公告)号：US20190139761A1

公开(公告)日：2019-05-09

申请号：US16306547

申请日：2017-06-02

申请人： IQE plc

发明人： Andrew Clark ,  Rytis Dargis ,  Michael Lebby ,  Rodney Pelzel

IPC分类号： H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267

摘要： A structure can include a III-N layer with a first lattice constant, a first rare earth pnictide layer with a second lattice constant epitaxially grown over the III-N layer, a second rare earth pnictide layer with a third lattice constant epitaxially grown over the first rare earth pnictide layer, and a semiconductor layer with a fourth lattice constant epitaxially grown over the second rare earth pnictide layer. A first difference between the first lattice constant and the second lattice constant and a second difference between the third lattice constant and the fourth lattice constant are less than one percent.

公开(公告)号：US10283357B2

公开(公告)日：2019-05-07

申请号：US15528871

申请日：2015-12-01

申请人： The University of Chicago

发明人： Dmitriy S. Dolzhnikov ,  Hao Zhang ,  Jaeyoung Jang ,  Jae Sung Son ,  Matthew G. Panthani ,  Dmitri V. Talapin

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/267 ,  C01B19/00 ,  H01L29/786 ,  H01L29/22

摘要： Chalcogenidometallates of group IIB, IV and V elements and, particularly, alkali metal-containing chalcogenidometallates of cadmium, lead and bismuth are provided. Also provided are methods of using the chalcogenidometallates as molecular solders to form metal chalcogenide structures, including thin films, molded objects and bonded surfaces composed of metal chalcogenides.

公开(公告)号：US10262900B2

公开(公告)日：2019-04-16

申请号：US15705856

申请日：2017-09-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Nicolas J. Loubet ,  Xin Miao ,  Alexander Reznicek

IPC分类号： H01L21/8234 ,  H01L21/84 ,  H01L21/268 ,  H01L21/324 ,  H01L29/78 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66 ,  H01L27/088

摘要： A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form device structures with a non-electrically active material. Selected device structures are masked with a block mask. Unmasked device structures are selectively annealed to increase electrical activity of the non-electrically active material to adjust a threshold voltage between the selected device structures and the unmasked device structures.

公开(公告)号：US20190109051A1

公开(公告)日：2019-04-11

申请号：US16196642

申请日：2018-11-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Ming-Heng TSAI ,  Chun-Sheng LIANG ,  Pei-Lin WU ,  Yi-Ren CHEN ,  Shih-Hsun CHANG

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L29/267 ,  H01L29/24 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/08

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack has a first upper portion and a first lower portion, and the first upper portion is wider than the first lower portion. The semiconductor device structure includes a spacer layer surrounding the gate stack. The spacer layer has a second upper portion and a second lower portion. The second upper portion is thinner than the second lower portion.

公开(公告)号：US10256327B2

公开(公告)日：2019-04-09

申请号：US15971225

申请日：2018-05-04

申请人： International Business Machines Corporation

发明人： Veeraraghavan S. Basker ,  Pouya Hashemi ,  Shogo Mochizuki ,  Alexander Reznicek

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/20 ,  H01L29/78 ,  H01L29/267 ,  H01L29/40 ,  H01L21/84 ,  H01L21/762 ,  H01L29/06

摘要： The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a first trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region.

公开(公告)号：US10249502B2

公开(公告)日：2019-04-02

申请号：US15004751

申请日：2016-01-22

申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

发明人： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-chen Yeh

IPC分类号： H01L21/336 ,  H01L21/285 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

摘要： Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

公开(公告)号：US20190097050A1

公开(公告)日：2019-03-28

申请号：US15832306

申请日：2017-12-05

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Mona A. Ebrish ,  Oleg Gluschenkov

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/267

CPC分类号： H01L29/7845 ,  H01L21/0245 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/267 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for reducing series resistance for transistors includes forming a conductive gate over and insulated from a semiconductor substrate, forming source and/or drain extension regions within the substrate and adjacent to respective source and/or drain regions, and forming source and/or drain regions within the substrate. The source and/or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions.

公开(公告)号：US20190097049A1

公开(公告)日：2019-03-28

申请号：US15714491

申请日：2017-09-25

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Mona A. Ebrish ,  Oleg Gluschenkov

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/267 ,  H01L21/02

摘要： A method for reducing series resistance for transistors includes forming a conductive gate over and insulated from a semiconductor substrate, forming source and/or drain extension regions within the substrate and adjacent to respective source and/or drain regions, and forming source and/or drain regions within the substrate. The source and/or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions.

公开(公告)号：US10236386B2

公开(公告)日：2019-03-19

申请号：US15843766

申请日：2017-12-15

申请人： The Board of Trustees of the University of Illinois

发明人： Wenjuan Zhu ,  Shang-Chun Lu ,  Mohamed Mohamed

IPC分类号： H01L21/00 ,  H01L29/00 ,  H01L29/786 ,  H01L29/24 ,  H01L21/02 ,  H01L29/15 ,  H01L29/66 ,  H01L29/267 ,  H01L29/739

摘要： The present disclosure provides vertical hetero- and homo-junction tunnel FET (TFET) based on multi-layer black phosphorus (BP) and transition metal dichalcogenides.

公开(公告)号：US10199269B2

公开(公告)日：2019-02-05

申请号：US15361503

申请日：2016-11-28

申请人： UNITED MICROELECTRONICS CORP.

发明人： Li-Han Chen ,  Yen-Tsai Yi ,  Chun-Chieh Chiu ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Hsin-Fu Huang

IPC分类号： H01L23/485 ,  H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78

摘要： A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.