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公开(公告)号：US11088026B2
公开(公告)日：2021-08-10
申请号：US16717564
申请日：2019-12-17
发明人： Kangguo Cheng , Nicolas J. Loubet , Xin Miao , Alexander Reznicek
IPC分类号： H01L21/8234 , H01L21/84 , H01L21/268 , H01L21/324 , H01L29/78 , H01L29/08 , H01L29/24 , H01L29/267 , H01L29/66 , H01L27/088
摘要： A device having co-integrated wimpy and nominal transistors includes first source/drain regions formed with a semiconductor alloy imparting strain into a first channel region. The device also has wimpy transistors including second source/drain regions formed with the semiconductor alloy that has been decomposed to include a larger amount of an electrically active atomic element than contained in the semiconductor alloy of the first source/drain region.
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公开(公告)号：US20200091237A1
公开(公告)日：2020-03-19
申请号：US16668116
申请日：2019-10-30
摘要： Embodiments of the invention are directed to a method and resulting structures for a steep-switch vertical field effect transistor (SS-VFET). In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source or drain region of a substrate. A top source or drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source or drain region. A bi-stable resistive system is formed on the top metallization layer. The bi-stable resistive system includes an insulator-to-metal transition material or a threshold-switching selector. The SS-VFET provides a subthreshold switching slope of less than 60 millivolts per decade.
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公开(公告)号：US10541272B2
公开(公告)日：2020-01-21
申请号：US15729758
申请日：2017-10-11
摘要： Embodiments of the invention are directed to a method and resulting structures for a steep-switch vertical field effect transistor (SS-VFET). In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source or drain region of a substrate. A top source or drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source or drain region. A bi-stable resistive system is formed on the top metallization layer. The bi-stable resistive system includes an insulator-to-metal transition material or a threshold-switching selector. The SS-VFET provides a subthreshold switching slope of less than 60 millivolts per decade.
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公开(公告)号：US20190096669A1
公开(公告)日：2019-03-28
申请号：US15715559
申请日：2017-09-26
发明人： Zhenxing Bi , Thamarai S. Devarajan , Nicolas J. Loubet , Binglin Miao , Muthumanickam Sankarapandian , Charan V. Surisetty , Chun W. Yeung , Jingyun Zhang
IPC分类号： H01L21/02
摘要： A method for forming a nanosheet semiconductor device includes forming a nanosheet stack comprising channel nanosheets. The method includes depositing silicon on the nanosheet stack, the silicon completely filling a space between adjacent channel nanosheets. The method includes etching the silicon. The method includes exposing the nanosheet stack to a gas phase heat treatment.
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5.发明申请公开(公告)号：US20180323278A1
公开(公告)日：2018-11-08
申请号：US16020475
申请日：2018-06-27
发明人： Bruce B. Doris , Hong He , Nicolas J. Loubet , Junli Wang
IPC分类号： H01L29/66 , H01L21/8238 , H01L21/265 , H01L29/78 , H01L29/423 , H01L29/10 , H01L27/092 , H01L29/165
摘要： A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.
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公开(公告)号：US09978678B1
公开(公告)日：2018-05-22
申请号：US15422544
申请日：2017-02-02
IPC分类号： H01L23/525 , H01L23/532 , H01L21/265 , H01L21/306 , H01L29/66 , H01L29/786
CPC分类号： H01L23/5256 , H01L21/265 , H01L21/30604 , H01L23/53209 , H01L23/53252 , H01L23/53266 , H01L23/53271 , H01L27/0629 , H01L27/1203 , H01L29/0673 , H01L29/4991 , H01L29/66787 , H01L29/78696
摘要： Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.
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公开(公告)号：US20180114833A1
公开(公告)日：2018-04-26
申请号：US15298737
申请日：2016-10-20
发明人： Ruqiang Bao , Michael A. Guillorn , Terence B. Hook , Nicolas J. Loubet , Robert R. Robison , Reinaldo A. Vega , Tenko Yamashita
IPC分类号： H01L29/06 , H01L21/306 , H01L29/423 , H01L29/08 , H01L29/10 , H01L29/786 , H01L27/088
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/823412 , H01L27/088 , H01L29/0653 , H01L29/0847 , H01L29/1033 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/786
摘要： Semiconductor devices and methods of making the same include forming a stack of alternating layers of channel material and sacrificial material. The sacrificial material is etched away to free the layers of channel material. A gate stack is formed around the layers of channel material. At least one layer of channel material is deactivated. Source and drain regions are formed in contact with the at least one layer of active channel material.
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公开(公告)号：US20180053853A1
公开(公告)日：2018-02-22
申请号：US15786037
申请日：2017-10-17
发明人： Kangguo Cheng , Nicolas J. Loubet , Xin Miao , Alexander Reznicek
IPC分类号： H01L29/78 , H01L21/8238 , H01L29/165 , H01L29/161 , H01L29/24 , H01L29/08 , H01L27/092 , H01L29/267
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823821 , H01L27/0924 , H01L29/785
摘要： A method of forming a semiconductor device that includes forming a strain relaxed buffer (SRB) layer atop a supporting substrate, and epitaxially forming a tensile semiconductor material atop a first portion of the strain relaxed buffer layer (SRB) layer. A second portion of the SRB layer is then removed, and a semiconductor material including a base material of silicon and phosphorus is formed atop a surface of the supporting substrate exposed by removing the second portion of the SRB layer. A compressive semiconductor material is epitaxially forming atop the semiconductor material including the base material of silicon and phosphorus. Compressive FinFET structures can then be formed from the compressive semiconductor material and tensile FinFET structures can then be formed from the tensile semiconductor material.
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公开(公告)号：US20170358677A1
公开(公告)日：2017-12-14
申请号：US15178010
申请日：2016-06-09
发明人： Kangguo Cheng , Nicolas J. Loubet , Xin Miao , Alexander Reznicek
IPC分类号： H01L29/78 , H01L27/092 , H01L29/165 , H01L29/267 , H01L29/161 , H01L21/8238 , H01L29/24 , H01L29/08
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823821 , H01L27/0924 , H01L29/785
摘要： A method of forming a semiconductor device that includes forming a strain relaxed buffer (SRB) layer atop a supporting substrate, and epitaxially forming a tensile semiconductor material atop a first portion of the strain relaxed buffer layer (SRB) layer. A second portion of the SRB layer is then removed, and a semiconductor material including a base material of silicon and phosphorus is formed atop a surface of the supporting substrate exposed by removing the second portion of the SRB layer. A compressive semiconductor material is epitaxially forming atop the semiconductor material including the base material of silicon and phosphorus. Compressive FinFET structures can then be formed from the compressive semiconductor material and tensile FinFET structures can then be formed from the tensile semiconductor material.
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公开(公告)号：US20170323949A1
公开(公告)日：2017-11-09
申请号：US15146325
申请日：2016-05-04
IPC分类号： H01L29/423 , H01L29/786 , H01L29/66 , H01L29/51 , H01L29/49 , H01L29/06 , H01L21/28
CPC分类号： H01L29/42392 , B82Y10/00 , H01L21/28088 , H01L21/28176 , H01L29/0673 , H01L29/1037 , H01L29/4966 , H01L29/518 , H01L29/66439 , H01L29/66772 , H01L29/775 , H01L29/78654 , H01L29/78696
摘要： A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrateforming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystallize the high-k dielectric layer.
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