公开(公告)号：US06365445B1

公开(公告)日：2002-04-02

申请号：US09846957

申请日：2001-05-01

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2184

CPC classification number: H01L29/66757 ,  H01L29/458 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78696

Abstract: For fabricating a field effect transistor on a buried insulating material in SOI (semiconductor on insulator) technology, a dielectric island is formed on the buried insulating material. An opening is etched through the buried insulating material at a location away from the dielectric island. An amorphous semiconductor material is deposited to fill the opening through the buried insulating material and to surround the dielectric island. The amorphous semiconductor material is polished until the top surface of the dielectric island is exposed and such that the amorphous semiconductor material surrounds the dielectric island. A layer of the amorphous semiconductor material is deposited on top of the dielectric island and on top of the amorphous semiconductor material surrounding the dielectric island. The amorphous semiconductor material surrounding the dielectric island and the layer of the amorphous semiconductor material are recrystallized to form a substantially single crystal structure of semiconductor material. A gate dielectric and a gate electrode of the field effect transistor are formed on top of a thinner portion of the semiconductor material disposed on the dielectric island. A drain extension region and a source extension region are formed by implanting a drain and source dopant into exposed regions of the thinner portion of the semiconductor material disposed on the dielectric island to minimize short channel effects. A drain contact region and a source contact region are formed from a thicker portion of the semiconductor material disposed to the sides of the dielectric island. The drain and source silicides are formed with the thicker drain and source contact regions to minimize parasitic resistance at the drain and source.

Abstract translation: 为了在SOI（绝缘体上半导体）技术的掩埋绝缘材料上制造场效应晶体管，在掩埋绝缘材料上形成介电岛。 在远离电介质岛的位置处通过掩埋绝缘材料蚀刻开口。 沉积非晶半导体材料以填充通过掩埋绝缘材料的开口并围绕电介质岛。 非晶半导体材料被抛光直到电介质岛的顶表面被暴露，并且非晶半导体材料围绕电介质岛。 非晶半导体材料的一层沉积在电介质岛的顶部上，并且在包围电介质岛的非晶半导体材料的顶部上。 围绕电介质岛的非晶半导体材料和非晶半导体材料层被重结晶以形成半导体材料的基本单晶结构。 场效应晶体管的栅极电介质和栅电极形成在设置在介质岛上的半导体材料的较薄部分的顶部。 通过将漏极和源极掺杂剂注入设置在介质岛上的半导体材料的较薄部分的暴露区域来形成漏极延伸区域和源延伸区域，以最小化短沟道效应。 漏极接触区域和源极接触区域由设置在电介岛的侧面的半导体材料的较厚部分形成。 漏极和源极硅化物形成有较厚的漏极和源极接触区域，以最小化漏极和源极处的寄生电阻。

公开(公告)号：US06342438B2

公开(公告)日：2002-01-29

申请号：US09187379

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L21265

CPC classification number: H01L21/823842 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823871

Abstract: A dual doped CMOS gate structure utilizes a nitrogen implant to suppress dopant inter-diffusion. The nitrogen implant is provided above standard trench isolation structures. Alternatively, an oxygen implant can be utilized. The use of the implant allows an increase in packing density for ultra-large-scale integrated (ULSI) circuits. The doping for N-channel and P-channel active regions can be completed when the polysilicon gate structures are doped.

Abstract translation: 双掺杂CMOS栅极结构利用氮注入来抑制掺杂剂相互扩散。 在标准沟槽隔离结构之上提供氮注入。 或者，可以使用氧注入。 使用植入物可以提高超大规模集成（ULSI）电路的封装密度。 当掺杂多晶硅栅极结构时，可以完成N沟道和P沟道有源区的掺杂。

公开(公告)号：US06284582B1

公开(公告)日：2001-09-04

申请号：US09398246

申请日：1999-09-17

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L218238

CPC classification number: H01L29/0895 ,  H01L27/0722 ,  H01L29/735

Abstract: A method of forming a metal oxide semiconductor (MOS)-controlled bipolar transistor includes tilt angle implanting a first impurity into a semiconductor substrate and implanting a second impurity into the semiconductor substrate to form an emitter and a collector. A corresponding transistor arranged as to combine the large current drive capacity of a bipolar junction transistor (BJT) with the smaller device size of a metal oxide semiconductor field effect transistor (MOSFET) is also provided. The transistor includes a semiconductor structure, a gate located proximate the semiconductor structure, a gate insulator disposed intermediate the semiconductor structure and the gate, a source region located in the semiconductor structure, a drain region located in the semiconductor structure, and a buffer region located in the semiconductor structure proximate the drain region.

Abstract translation: 形成金属氧化物半导体（MOS）控制的双极晶体管的方法包括将第一杂质注入到半导体衬底中并将第二杂质注入到半导体衬底中以形成发射极和集电极的倾斜角。 还提供了将双极结型晶体管（BJT）的大电流驱动能力与金属氧化物半导体场效应晶体管（MOSFET）的较小器件尺寸组合的相应晶体管。 晶体管包括半导体结构，位于半导体结构附近的栅极，设置在半导体结构和栅极之间的栅极绝缘体，位于半导体结构中的源极区域，位于半导体结构中的漏极区域和位于半导体结构中的缓冲区域 在靠近漏极区域的半导体结构中。

公开(公告)号：US06265293B1

公开(公告)日：2001-07-24

申请号：US09384121

申请日：1999-08-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21425

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/7833

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region is between 10-15 nm below the top surface of the substrate, and the deep amorphous region is between 150-200 nm below the top surface of the substrate. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs). A step separate from the annealing step for the source/drain regions is utilized for annealing the gate conductor.

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法采用双非晶化技术。 该技术产生了300nm厚的浅非晶区和深非晶区。 浅非晶区域在衬底的顶表面之下10-15nm之间，深非晶区域在衬底顶表面之下的150-200nm之间。 该过程可用于P沟道或N沟道金属氧化物半导体场效应晶体管（MOSFET）。 与源极/漏极区域的退火步骤分离的步骤用于退火栅极导体。

公开(公告)号：US06265291B1

公开(公告)日：2001-07-24

申请号：US09224754

申请日：1999-01-04

Applicant: Bin Yu ,  Emi Ishida

Inventor： Bin Yu ,  Emi Ishida

IPC: H01L2104

CPC classification number: H01L21/28518 ,  H01L21/26506

Abstract: A method of manufacturing an integrated circuit to optimize the contact resistance between impurity diffusing layers and silicide is disclosed herein. The method includes implanting a first material to a layer of semiconductor to create a buried amorphous silicon layer; implanting a second material in the layer of semiconductor and buried amorphous layer, forming a dopant profile region with a curved shape; depositing a layer of metal on the layer of semiconductor; melting the buried amorphous layer to reconfigure the curved shape to a substantially vertical profile of maximum dopant concentration; and forming silicide with the layer of semiconductor and layer of metal, the bottom of the silicide located in the vertical shape on the dopant profile region.

Abstract translation: 本文公开了制造用于优化杂质扩散层和硅化物之间的接触电阻的集成电路的方法。 该方法包括将第一材料注入到半导体层中以产生埋入的非晶硅层; 将第二材料注入到半导体层和埋入非晶层中，形成具有弯曲形状的掺杂剂分布区域; 在半导体层上沉积金属层; 熔化埋入的非晶层以将弯曲形状重新配置为最大掺杂剂浓度的基本垂直分布; 并且用半导体层和金属层形成硅化物，硅化物的底部位于掺杂物分布区域上的垂直形状。

公开(公告)号：US06265256B1

公开(公告)日：2001-07-24

申请号：US09156238

申请日：1998-09-17

Applicant: Judy Xilin An ,  Bin Yu ,  Yowjuang W. Liu

Inventor： Judy Xilin An ,  Bin Yu ,  Yowjuang W. Liu

IPC: H01L218238

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L21/823468 ,  H01L29/6659

Abstract: A method for making a ULSI MOSFET includes establishing a gate void in a field oxide layer above a silicon substrate, after source and drain regions with associated source and drain extensions have been established in the substrate. A gate electrode is deposited in the void and gate spacers are likewise deposited in the void on the sides of the gate electrode, such that the gate electrode is spaced from the walls of the void. The spacers, not the gate electrode, are located above the source/drain extensions, such that fringe coupling between the gate electrode and the source and drain extensions is suppressed.

Abstract translation: 制造ULSI MOSFET的方法包括：在衬底中建立具有相关源极和漏极延伸部分的源极和漏极区域之后，在硅衬底上的场氧化物层中建立栅极空隙。 栅电极沉积在空隙中，并且栅极间隔物同样沉积在栅电极的侧面上的空隙中，使得栅电极与空隙的壁间隔开。 间隔件而不是栅电极位于源极/漏极延伸部上方，从而抑制栅极电极和源极和漏极延伸部之间的边缘耦合。

公开(公告)号：US06262456B1

公开(公告)日：2001-07-17

申请号：US09187842

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L31113

CPC classification number: H01L29/6659 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/0922 ,  H01L27/105 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures with a polysilicon material. The polysilicon material is implanted with lower concentrations of germanium where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV.

Abstract translation: 超大规模集成（ULSI）电路包括具有不同阈值电压但具有相同通道特性的MOSFET。 MOSFET包括具有多晶硅材料的栅极结构。 用较低浓度的锗注入多晶硅材料，其中需要较低的阈值电压MOSFET。 在锗的0-60％浓度范围内，阈值电压可以改变大约240mV。

公开(公告)号：US06255174B1

公开(公告)日：2001-07-03

申请号：US09334121

申请日：1999-06-15

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/7835

Abstract: The inventive method and apparatus provides improved semiconductor devices, such as MOSFET's with a delayed threshold voltage roll-off and short channel effects, making the semiconductor devices more tolerant of gate variations for short gate length devices. The invention provides a semiconductor device with an asymmetric channel doping profile. A first pocket dopant implantation with a 0° tilt is used to create a first source dopant pocket and a drain dopant pocket. A second pocket dopant implantation with a 30-60° tilt creates a second source dopant pocket without creating an additional drain dopant pocket, thus creating the asymmetric doping profile.

Abstract translation: 本发明的方法和装置提供改进的半导体器件，例如具有延迟的阈值电压滚降和短沟道效应的MOSFET，使半导体器件更容忍对于短栅极长度器件的栅极变化。 本发明提供了具有不对称沟道掺杂分布的半导体器件。 使用具有0°倾斜的第一种杂质掺杂剂注入来产生第一源掺杂剂阱和漏极掺杂剂袋。 具有30-60°倾斜的第二袋式掺杂剂注入产生第二源掺杂剂袋而不产生附加的漏极掺杂剂袋，从而产生不对称掺杂分布。

公开(公告)号：US6087235A

公开(公告)日：2000-07-11

申请号：US418276

申请日：1999-10-14

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21/336 ,  H01L29/08

CPC classification number: H01L29/66628 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/66545

Abstract: A field effect transistor is fabricated to have elevated drain and source contact structures with prevention of short-channel effects and leakage current which may result due to the formation of facetted surfaces on the elevated drain and source contact structures near the gate of the field effect transistor. The field effect transistor includes a drain extension implant, a source extension implant, a gate dielectric, a gate structure disposed over the gate dielectric, and a first spacer disposed on sidewalls of the gate dielectric and of the gate structure. An elevated drain contact structure is selectively grown on the drain extension implant and has a drain facetted surface facing toward the first spacer on the sidewall of the gate structure. Similarly, an elevated source contact structure is selectively grown on the source extension implant and has a source facetted surface facing toward the first spacer on the sidewall of the gate structure. A second spacer is formed to cover the drain facetted surface and the source facetted surface before dopant implantation into and silicide formation on the elevated drain and source contact structures. In this manner, the dopant is prevented from being implanted into the drain facetted surface and the source facetted surface such that short-channel effects are minimized in the field effect transistor of the present invention. In addition, formation of silicide on the drain facetted surface and the source facetted surface is prevented to minimize leakage current through the drain and source extension implants of the field effect transistor of the present invention.

Abstract translation: 制造场效应晶体管具有升高的漏极和源极接触结构，防止短沟道效应和漏电流，这可能是由于在场效应晶体管的栅极附近的升高的漏极和源极接触结构上形成刻面 。 场效应晶体管包括漏极延伸注入，源极延伸注入，栅极电介质，设置在栅极电介质上的栅极结构，以及设置在栅极电介质和栅极结构的侧壁上的第一间隔物。 升高的漏极接​​触结构选择性地生长在漏极延伸植入物上，并且具有面向栅极结构的侧壁上的第一间隔物的漏极分面表面。 类似地，升高的源极接触结构选择性地生长在源极延伸植入物上，并且具有面向栅极结构的侧壁上的第一间隔物的源极分面。 形成第二间隔物以在掺杂剂注入到高架漏极和源极接触结构之间的硅化物形成之前覆盖漏极分面和源极面表面。 以这种方式，防止了掺杂剂被注入到漏极刻面和源极刻面中，使得在本发明的场效应晶体管中短沟道效应最小化。 此外，防止在漏极表面和源极面上形成硅化物以使通过本发明的场效应晶体管的漏极和源延伸注入的漏电流最小化。

公开(公告)号：US6015999A

公开(公告)日：2000-01-18

申请号：US39926

申请日：1998-03-16

Applicant: Bin Yu ,  Chenming Hu ,  Ya-Chin King ,  Jeffrey T. Pohlman ,  Rita Trivedi

Inventor： Bin Yu ,  Chenming Hu ,  Ya-Chin King ,  Jeffrey T. Pohlman ,  Rita Trivedi

IPC: H01L29/861 ,  H01L29/866 ,  H01L29/00

CPC classification number: H01L29/8618 ,  H01L29/861 ,  H01L29/866

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p- region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm.sup.-3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p- layer should be between about 0.5E14 cm.sup.-3 and about 1.OE17 cm.sup.-3. The junction depth of the fourth (n+) region should be greater than about 0.3 .mu.m. The thickness of the third (p+) region should be between about 0.3 .mu.m and about 2.0 .mu.m, and the thickness of the second (p-) region should be between about 0.5 .mu.m and about 5.0 .mu.m.

Abstract translation: 穿通二极管瞬态抑制器件具有改变掺杂浓度的基极区域，以改善泄漏和钳位特性。 穿通二极管包括包括n +区域的第一区域，包括邻接第一区域的p-区域的第二区域，包括邻接第二区域的p +区域的第三区域，以及包括邻接第三区域的n +区域的第四区域 地区。 n +层的峰值掺杂剂浓度应为约1.5E18cm-3，p +层的峰值掺杂剂浓度应在n +层的峰值浓度的约1至约5倍之间， 层应在约0.5E14cm-3和约1.0E17cm-3之间。 第四（n +）区域的结深度应大于约0.3μm。 第三（p +）区域的厚度应在约0.3μm至约2.0μm之间，第二（p-）区域的厚度应在约0.5μm至约5.0μm之间。