公开(公告)号：US07394132B2

公开(公告)日：2008-07-01

申请号：US11180890

申请日：2005-07-13

申请人： Yowjuang W. Liu ,  Minchang Liang

发明人： Yowjuang W. Liu ,  Minchang Liang

IPC分类号： H01L23/62

CPC分类号： H01L27/1203 ,  H01L27/0288 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) includes one or more silicon-on-insulator (SOI) transistors. Each SOI transistor includes a first source region, a second source region, a drain region, a body contact region, a gate, and first and second isolation regions. The body contact region couples electrically to a body of the SOI transistor. The gate controls current flow between the first and second source regions and a drain region of the transistor. The first isolation region is disposed between the first source region and the body contact region. The second isolation region is disposed between the second source region and the body contact region.

摘要翻译： 集成电路（IC）包括一个或多个绝缘体上硅（SOI）晶体管。 每个SOI晶体管包括第一源极区域，第二源极区域，漏极区域，体接触区域，栅极以及第一和第二隔离区域。 体接触区域电耦合到SOI晶体管的主体。 栅极控制第一和第二源极区域与晶体管的漏极区域之间的电流。 第一隔离区域设置在第一源区域和身体接触区域之间。 第二隔离区域设置在第二源区域和身体接触区域之间。

公开(公告)号：US06525381B1

公开(公告)日：2003-02-25

申请号：US09541127

申请日：2000-03-31

申请人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

发明人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

IPC分类号： H01L2976

CPC分类号： H01L29/66772 ,  H01L29/41733 ,  H01L29/78612 ,  H01L29/78624

摘要： A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

摘要翻译： 半导体器件包括具有源极，主体和漏极区域的半导体层的晶片。 半导体区域的导电区域与源极区域和体区域重叠并电耦合。 源极和体区的电耦合减少了半导体器件中的浮体效应。 构造半导体器件的方法利用间隔物，掩模和/或倾斜注入来形成与半导体层的源极和体区域重叠的源极体导电区域，以及位于半导体器件的内部的漏极导电区域 漏极区域。

公开(公告)号：US06326310B1

公开(公告)日：2001-12-04

申请号：US08992623

申请日：1997-12-17

申请人： Mark S. Chang ,  Yowjuang W. Liu

发明人： Mark S. Chang ,  Yowjuang W. Liu

IPC分类号： H01L21311

CPC分类号： H01L21/3086 ,  H01L21/76232

摘要： A system and method for providing a trench in a material using semiconductor processing is disclosed. In one aspect, the method and system include (a) providing a spacer, (b) etching the material, and (c) repeating steps (a) and (b) a sufficient number of times to achieve a desired profile for the trench. The spacer is insensitive to an etch of the material. The material is exposed adjacent to the spacer. In another aspect, the method and system include (a) providing a spacer, (b) etching the material, (c) stripping the spacer, and (d) repeating steps (a) through (c) until a desired profile for the trench is achieved. Each time steps (a) through (c) are repeated via step (d), a thinner spacer is provided. In addition, the spacer is insensitive to an etch of the material. The material is exposed adjacent to the spacer.

摘要翻译： 公开了一种使用半导体处理在材料中提供沟槽的系统和方法。 在一个方面，该方法和系统包括（a）提供间隔物，（b）蚀刻该材料，和（c）重复步骤（a）和（b）足够的次数以达到沟槽所需的轮廓。 间隔物对材料的蚀刻不敏感。 材料与间隔物相邻地露出。 在另一方面，该方法和系统包括（a）提供间隔物，（b）蚀刻该材料，（c）剥离间隔物，和（d）重复步骤（a）至（c）直到沟槽的期望曲线 已完成。 每次通过步骤（d）重复步骤（a）至（c）时，提供更薄的间隔物。 此外，间隔物对材料的蚀刻不敏感。 材料与间隔物相邻地露出。

公开(公告)号：US06309919B1

公开(公告)日：2001-10-30

申请号：US09237001

申请日：1999-01-25

申请人： Yowjuang W. Liu ,  Donald L. Wollesen

发明人： Yowjuang W. Liu ,  Donald L. Wollesen

IPC分类号： H01L218238

CPC分类号： H01L29/7827 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78642

摘要： Complementary metal-oxide-semiconductor (CMOS) transistors (18,22) are formed with vertical channel regions (30,52) on an insulator substrate (14). Highly doped polysilicon gates (44,68) are formed in trenches (36,58) to extend laterally around the channel regions (30,52) as insulatively displaced therefrom by gate insulators (41,62) that are grown on the sidewalls of the trenches (36,58). The transistors (18,22), which are formed in respective mesas (20,24) have deeply implanted source regions (28,50) that are ohmically connected to the semiconductor surface via respective source connector regions (34,70).

摘要翻译： 互补金属氧化物半导体（CMOS）晶体管（18,22）在绝缘体衬底（14）上形成有垂直沟道区（30,52）。 高度掺杂多晶硅栅极（44,68）形成在沟槽（36,58）中，以通过栅极绝缘体（41,62）从沟槽区域（30,52）的侧壁上生长的绝缘体（41,62）绝缘地从沟槽区域（30,52）横向延伸， 沟槽（36,58）。 形成在相应的台面（20,24）中的晶体管（18,22）具有通过相应的源连接器区域（34,70）欧姆连接到半导体表面的深度注入的源极区域（28,50）。

公开(公告)号：US06303437B1

公开(公告)日：2001-10-16

申请号：US09632536

申请日：2000-08-04

申请人： Yowjuang W. Liu

发明人： Yowjuang W. Liu

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/7883

摘要： A non-volatile semiconductor device structure and method for low power applications comprises a trenched floating gate and corner dopings and further includes a well junction region with a source region and a drain region therein, and includes a channel region, an inter-gate dielectric layer, and a control gate. The trenched floating gate is formed in a trench etched into the semiconductor substrate and has a top surface which is substantially planar with a top surface of the semiconductor substrate. The source and drain regions are laterally separated by the trench in which the trenched floating gate is formed and have a depth which is approximately less than the depth of the trench. The channel region is formed beneath a bottom surface of the trench and is doped to form a depletion type channel region. Corner dopings are diffusion regions formed adjacent to the source and drain regions of the semiconductor substrate and are immediately contiguous the upper vertical sides of the trench and the substrate surface.

摘要翻译： 用于低功率应用的非易失性半导体器件结构和方法包括沟槽浮栅和角掺杂，并且还包括其中具有源极区和漏极区的阱结区域，并且包括沟道区，栅极间介电层 ，和一个控制门。 沟槽浮栅形成在蚀刻到半导体衬底中的沟槽中，并且具有与半导体衬底的顶表面基本平坦的顶表面。 源极和漏极区域被形成沟槽的浮动栅极的沟槽横向分开，并且具有大致小于沟槽深度的深度。 沟道区形成在沟槽的底表面之下，并被掺杂以形成耗尽型沟道区。 角部掺杂是与半导体衬底的源极和漏极区相邻形成的扩散区，并且立即与沟槽和衬底表面的上部垂直侧邻接。

公开(公告)号：US06225659B1

公开(公告)日：2001-05-01

申请号：US09052058

申请日：1998-03-30

申请人： Yowjuang W. Liu

发明人： Yowjuang W. Liu

IPC分类号： H01L2976

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/7883

摘要： A non-volatile semiconductor device structure and method for low power applications comprises a trenched floating gate and corner dopings and further includes a well junction region with a source region and a drain region therein, and includes a channel region, an inter-gate dielectric layer, and a control gate. The trenched floating gate is formed in a trench etched into the semiconductor substrate and has a top surface which is substantially planar with a top surface of the semiconductor substrate. The source and drain regions are laterally separated by the trench in which the trenched floating gate is formed and have a depth which is approximately less than the depth of the trench. The channel region is formed beneath a bottom surface of the trench and is doped to form a depletion type channel region. Corner dopings are diffusion regions formed adjacent to the source and drain regions of the semiconductor substrate and are immediately contiguous the upper vertical sides of the trench and the substrate surface.

摘要翻译： 用于低功率应用的非易失性半导体器件结构和方法包括沟槽浮栅和角掺杂，并且还包括其中具有源极区和漏极区的阱结区域，并且包括沟道区，栅极间介电层 ，和一个控制门。 沟槽浮栅形成在蚀刻到半导体衬底中的沟槽中，并且具有与半导体衬底的顶表面基本平坦的顶表面。 源极和漏极区域被形成沟槽的浮动栅极的沟槽横向分开，并且具有大致小于沟槽深度的深度。 沟道区形成在沟槽的底表面之下，并被掺杂以形成耗尽型沟道区。 角部掺杂是与半导体衬底的源极和漏极区相邻形成的扩散区，并且立即与沟槽和衬底表面的上部垂直侧邻接。

公开(公告)号：US6093967A

公开(公告)日：2000-07-25

申请号：US992573

申请日：1997-12-17

申请人： Yowjuang W. Liu ,  Mark S. Chang ,  Michael K. Templeton

发明人： Yowjuang W. Liu ,  Mark S. Chang ,  Michael K. Templeton

IPC分类号： H01L21/285 ,  H01L23/54 ,  H01L21/441

CPC分类号： H01L21/28518

摘要： Self-aligned silicide contacts having a height that is at least about equal to the gate height are formed by depositing silicon over active regions of the substrate, depositing a refractory metal over the silicon, and heating the silicon and the refractory metal. The deposited silicon may be amorphous silicon in which case the deposition temperature can be as low as 580.degree. C. If polysilicon is deposited, the deposition temperature has to be at least 620.degree. C.

摘要翻译： 通过在衬底的有源区上沉积硅，在硅上沉积难熔金属，并加热硅和难熔金属，形成具有至少约等于栅极高度的高度的自对准硅化物触点。 沉积的硅可以是非晶硅，在这种情况下，沉积温度可以低至580℃。如果沉积多晶硅，则沉积温度必须至少为620℃。

公开(公告)号：US6064104A

公开(公告)日：2000-05-16

申请号：US594209

申请日：1996-01-31

申请人： Farrokh Omid-Zohoor ,  Yowjuang W. Liu

发明人： Farrokh Omid-Zohoor ,  Yowjuang W. Liu

IPC分类号： H01L21/762 ,  H01L29/00

CPC分类号： H01L21/76227 ,  H01L21/76224

摘要： A trench isolation structure in a semiconductor substrate includes a trench opening in the surface of the substrate and a seamless oxide layer filling the trench. The seamless oxide layer is formed by forming a first oxide layer in the trench, adding a silicon material overlying the first oxide layer and within a gap on the first oxide layer between the trench sidewalls that tend to be produced in the preceding step, and oxidizing the silicon material to form a second oxide layer. The deposited silicon material expands during oxidation, filling the trench opening to produce a seamless oxide fill of the trench. This seamless trench isolation structure prevents accumulation of materials that reduce the yield of the finished semiconductor product.

摘要翻译： 半导体衬底中的沟槽隔离结构包括在衬底的表面中的沟槽开口和填充沟槽的无缝氧化物层。 无缝氧化物层通过在沟槽中形成第一氧化物层而形成，在第一氧化物层上面加上硅材料，并且在前述步骤中容易产生的沟槽侧壁之间的第一氧化物层上的间隙内加氧化 所述硅材料形成第二氧化物层。 沉积的硅材料在氧化期间膨胀，填充沟槽开口以产生沟槽的无缝氧化物填充物。 这种无缝沟槽隔离结构防止了降低成品半导体产品的产量的材料的堆积。

公开(公告)号：US5940718A

公开(公告)日：1999-08-17

申请号：US119715

申请日：1998-07-20

申请人： Effiong Ibok ,  Yue-Song He ,  Yowjuang W. Liu

发明人： Effiong Ibok ,  Yue-Song He ,  Yowjuang W. Liu

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： A method for fabricating a semiconductor device including a silicon substrate and plural silicon stacks thereon includes forming a nitride shield layer on the substrate and stacks to cover the stacks, such that the stacks are protected from loss of critical dimension during subsequent isolation trench formation and oxidation. In other words, the edge of each stack, and thus the critical dimension of the silicon layers of the stack, is protected from oxidation by the nitride shield layer.

摘要翻译： 一种用于制造包括硅衬底和其上的多个硅堆叠的半导体器件的方法包括在衬底上形成氮化物屏蔽层并堆叠以覆盖堆叠，使得在随后的隔离沟槽形成和氧化期间保护堆叠免受临界尺寸的损失 。 换句话说，每个堆叠的边缘以及因此堆叠的硅层的临界尺寸被氮化物屏蔽层防止氧化。

公开(公告)号：US5932911A

公开(公告)日：1999-08-03

申请号：US766494

申请日：1996-12-13

申请人： John T. Yue ,  Matthew S. Buynoski ,  Yowjuang W. Liu ,  Peng Fang

发明人： John T. Yue ,  Matthew S. Buynoski ,  Yowjuang W. Liu ,  Peng Fang

IPC分类号： H01L21/265 ,  H01L21/335 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/66636 ,  B82Y10/00 ,  H01L21/26586 ,  H01L29/41766 ,  H01L29/66439 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854

摘要： A field effect transistor is formed across one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.

摘要翻译： 跨越一个或多个沟槽（26）或条（120）形成场效应晶体管，从而增加了沟道区的有效宽度和器件的载流能力。