公开(公告)号：US06501522B2

公开(公告)日：2002-12-31

申请号：US09907041

申请日：2001-07-17

申请人： Wei-Chih Chang ,  Hsin Ming Chen ,  Yun-Chieh Yuan ,  Yao-Nan Chen

发明人： Wei-Chih Chang ,  Hsin Ming Chen ,  Yun-Chieh Yuan ,  Yao-Nan Chen

IPC分类号： G02F11335

CPC分类号： G02F1/133553

摘要： A method of fabricating a reflective type LCD, having the steps of: (a)providing a substrate; (b) forming a polymer resin layer on the substrate; (c) forming a positive-type photoresist layer on the polymer resin layer, wherein the upper surface of the photoresist layer has a convex/concave profile; and (d)performing a dry etching process to completely remove the photoresist layer and partially remove the polymer resin layer so as to shape the upper surface of the polymer resin layer into a convex/concave profile.

摘要翻译： 一种制造反射型LCD的方法，具有以下步骤：（a）提供衬底; （b）在基板上形成聚合物树脂层; （c）在聚合物树脂层上形成正型光致抗蚀剂层，其中光致抗蚀剂层的上表面具有凸/凹形状; 和（d）进行干蚀刻处理以完全除去光致抗蚀剂层并部分地除去聚合物树脂层，以将聚合物树脂层的上表面形成为凸/凹形轮廓。

公开(公告)号：US06372525B1

公开(公告)日：2002-04-16

申请号：US09467133

申请日：1999-12-20

申请人： Chrong Jung Lin ,  Hsin Ming Chen

发明人： Chrong Jung Lin ,  Hsin Ming Chen

IPC分类号： H01L2166

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test structure for evaluating plasma damage in thin gate oxides is formed with a single polysilicon floating gate EEPROM device on which an antenna structure delivers charge to a floating gate through a tunnel oxide. The floating gate extends beyond the MOSFET channel in one direction, passing over field oxide and terminating in a pad over a thin tunnel oxide window formed over an isolated n+ diffusion. The n+ diffusion is connected to a metal antenna structure which is exposed to a processing plasma. Charge accumulated on the antenna during plasma exposure causes a tunnel current to flow through the tunnel oxide, and charge to accumulate on the floating gate. A second extension of the polysilicon floating gate passes over a second field oxide region and terminates in a pad over a thicker oxide formed on a second isolated n+ diffusion. The second n+ diffusion forms the control gate of the EEPROM and is connected by wiring to a probe pad. The device is formed in the saw-kerf region of a product wafer. After exposure of the device to plasma processing, the device is tested in-line with conventional probe testing equipment. Threshold voltage is measured by applying a scanning voltage to the control gate of the EEPROM. The device is capable of determining polarity and magnitude of charge accumulated on the gate from the plasma and is able to distinguish the degree of plasma damage incurred by various plasma processes. The test device has a greater sensitivity than other plasma sensing devices because the threshold voltage can be amplified by the EEPROM.

摘要翻译： 用于评估薄栅氧化物中的等离子体损伤的测试结构由单个多晶硅浮置栅极EEPROM器件形成，其中天线结构通过隧道氧化物将电荷传递到浮置栅极。 浮置栅极在一个方向上延伸超过MOSFET沟道，通过场氧化物并终止于在隔离的n +扩散上形成的薄隧道氧化物窗口上的焊盘。 n +扩散连接到暴露于处理等离子体的金属天线结构。 在等离子体暴露期间累积在天线上的电荷导致隧道电流流过隧道氧化物，并且电荷积聚在浮动栅极上。 多晶硅浮栅的第二延伸通过第二场氧化物区，并终止在形成于第二隔离n +扩散上的较厚氧化物上的焊盘中。 第二个n +扩散形成EEPROM的控制栅极，并通过布线连接到探针焊盘。 该装置形成在产品晶片的锯切区域中。 在将设备暴露于等离子体处理之后，该装置与常规探针测试设备一起进行测试。 通过向EEPROM的控制栅极施加扫描电压来测量阈值电压。 该装置能够确定从等离子体积聚在栅极上的电荷的极性和幅度，并且能够区分由各种等离子体处理引起的等离子体损伤的程度。 测试装置具有比其他等离子体感测装置更大的灵敏度，因为阈值电压可以被EEPROM放大。

公开(公告)号：US08941167B2

公开(公告)日：2015-01-27

申请号：US13415185

申请日：2012-03-08

申请人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Shih-Chen Wang ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Shih-Chen Wang ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： H01L29/788

CPC分类号： H01L29/42328 ,  G11C16/0408 ,  H01L27/11558 ,  H01L29/7885

摘要： An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.

摘要翻译： 可擦除可编程单一多晶硅非易失性存储器包括包括选择栅极，第一p型掺杂区域和第二p型掺杂区域的第一PMOS晶体管，其中选择栅极连接到选择栅极电压，并且第一 p型掺杂区域连接到源极线电压; 包括第二p型掺杂区的第二PMOS晶体管，第三p型掺杂区和浮置栅，其中第三p型掺杂区连接到位线电压; 以及与浮置栅极相邻的擦除栅极区域，其中擦除栅极区域连接到擦除线电压。

公开(公告)号：US08681528B2

公开(公告)日：2014-03-25

申请号：US13590392

申请日：2012-08-21

申请人： Meng-Yi Wu ,  Yueh-Chia Wen ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Meng-Yi Wu ,  Yueh-Chia Wen ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  H01L27/11206

摘要： A one-bit memory cell for a nonvolatile memory includes a bit line and a plurality of serially-connected storage units. The bit line is connected to the serially-connected storage units. Each storage unit includes a first doped region, a second doped region and a third doped region, which are formed in a surface of a substrate. A first gate structure is disposed over a first channel region between the first doped region and the second doped region. The first gate structure is connected to a control signal line. A second gate structure is disposed over a second channel region between the second doped region and the third doped region. The second gate structure is connected to an anti-fuse signal line.

摘要翻译： 用于非易失性存储器的一位存储单元包括位线和多个串联存储单元。 位线连接到串行存储单元。 每个存储单元包括形成在基板的表面中的第一掺杂区域，第二掺杂区域和第三掺杂区域。 第一栅极结构设置在第一掺杂区域和第二掺杂区域之间的第一沟道区域上。 第一栅极结构连接到控制信号线。 第二栅极结构设置在第二掺杂区域和第三掺杂区域之间的第二沟道区域上。 第二栅极结构连接到反熔丝信号线。

公开(公告)号：US20140056051A1

公开(公告)日：2014-02-27

申请号：US13590392

申请日：2012-08-21

申请人： Meng-Yi Wu ,  Yueh-Chia Wen ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Meng-Yi Wu ,  Yueh-Chia Wen ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C17/12 ,  G11C17/00

CPC分类号： G11C17/16 ,  H01L27/11206

摘要： A one-bit memory cell for a nonvolatile memory includes a bit line and a plurality of serially-connected storage units. The bit line is connected to the serially-connected storage units. Each storage unit includes a first doped region, a second doped region and a third doped region, which are formed in a surface of a substrate. A first gate structure is disposed over a first channel region between the first doped region and the second doped region. The first gate structure is connected to a control signal line. A second gate structure is disposed over a second channel region between the second doped region and the third doped region. The second gate structure is connected to an anti-fuse signal line.

摘要翻译： 用于非易失性存储器的一位存储器单元包括位线和多个串联存储单元。 位线连接到串行存储单元。 每个存储单元包括形成在基板的表面中的第一掺杂区域，第二掺杂区域和第三掺杂区域。 第一栅极结构设置在第一掺杂区域和第二掺杂区域之间的第一沟道区域上。 第一栅极结构连接到控制信号线。 第二栅极结构设置在第二掺杂区域和第三掺杂区域之间的第二沟道区域上。 第二栅极结构连接到反熔丝信号线。

公开(公告)号：US08363475B2

公开(公告)日：2013-01-29

申请号：US12750650

申请日：2010-03-30

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： H01L27/088 ,  G11C16/0458 ,  G11C16/28 ,  G11C16/3418

摘要： A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.

摘要翻译： 非易失性存储单元包括第一晶体管对以及第一和第二控制栅极。 第一晶体管对包括串联和相同类型的第一和第二晶体管。 第一和第二晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极。 第一控制栅极通过隧道结耦合到第一浮动多晶硅栅极，并且第二控制栅极通过另一隧道结耦合到第二浮动多晶硅栅极。

公开(公告)号：US20120134205A1

公开(公告)日：2012-05-31

申请号：US13366370

申请日：2012-02-06

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： H01L21/28282 ,  G11C16/10 ,  H01L27/11206 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.

摘要翻译： 提供了一种用于存储单元的操作方法，其中存储单元包括阱区，选择栅极，第一栅极，第二栅极，氧化物氮化物间隔物，第一扩散区域和第二扩散区域。 存储单元的操作方法包括以下步骤。 在编程操作期间，击穿电压通过形成在选择栅极下方的第一沟道区域耦合到第二扩散区域。 编程电压被顺序地或同时地施加到第一栅极和第二栅极以破裂第一氧化物层和第二氧化物层，其中第一氧化物层设置在第一栅极和阱区域之间，第二氧化物层是 设置在第二栅极和阱区域之间。

公开(公告)号：US20110299336A1

公开(公告)日：2011-12-08

申请号：US12792746

申请日：2010-06-03

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Ching-Sung Yang

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L27/11558 ,  G11C16/0433 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.

摘要翻译： 提供具有浮置栅晶体管，编程门和控制栅极的单多晶硅层非易失性存储器。 浮栅晶体管具有浮置栅极和隧穿介电层。 浮栅设置在基板上。 隧道介电层设置在浮置栅极和衬底之间。 编程栅极，控制栅极和擦除栅极分别设置在由隧道电介质层分离的浮置栅极下的衬底中。 因此，在编程操作和擦除操作期间，通过隧道介电层的不同区域注入和排出电荷，以增加非易失性存储器的可靠性。

公开(公告)号：US20110242893A1

公开(公告)日：2011-10-06

申请号：US12750650

申请日：2010-03-30

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： H01L27/088 ,  G11C16/0458 ,  G11C16/28 ,  G11C16/3418

摘要： A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.

摘要翻译： 非易失性存储单元包括第一晶体管对以及第一和第二控制栅极。 第一晶体管对包括串联和相同类型的第一和第二晶体管。 第一和第二晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极。 第一控制栅极通过隧道结耦合到第一浮动多晶硅栅极，并且第二控制栅极通过另一隧道结耦合到第二浮动多晶硅栅极。

公开(公告)号：US07855417B2

公开(公告)日：2010-12-21

申请号：US11833235

申请日：2007-08-03

申请人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L29/786 ,  H01L29/792

CPC分类号： H01L27/115

摘要： A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the conductive type silicon body layer beneath the gate.

摘要翻译： 设置在SOI衬底中的非易失性存储器。 非易失性存储器包括存储单元和第一导电类型掺杂区域。 存储单元包括栅极，电荷存储结构，底部电介质层，第二导电类型漏极区域和第二导电型源极区域。 栅极设置在SOI衬底上。 电荷存储结构设置在栅极和SOI衬底之间。 底部电介质层设置在电荷存储层和SOI衬底之间。 第二导电型漏极区域和第二导电型源极区域设置在栅极的两侧旁边的第一导电型硅体层中。 第一导电型掺杂区域设置在第一导电型硅体层中，并且电连接到栅极下方的导电型硅体层。