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    Mirroring Data Between Redundant Storage Controllers Of A Storage System
    101.
    发明申请
    Mirroring Data Between Redundant Storage Controllers Of A Storage System 有权
    在存储系统的冗余存储控制器之间镜像数据

    公开(公告)号：US20110131373A1

    公开(公告)日：2011-06-02

    申请号：US12627440

    申请日：2009-11-30

    Applicant: Pankaj Kumar ,  Hang T. Nguyen ,  Mark Yarch ,  Timothy J. Jehl ,  John A. Miller

    Inventor： Pankaj Kumar ,  Hang T. Nguyen ,  Mark Yarch ,  Timothy J. Jehl ,  John A. Miller

    IPC: G06F12/08 ,  G06F12/00 ,  G06F12/16

    CPC classification number: G06F11/2089 ,  G06F11/2097

    Abstract: In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括用于控制包括多个盘的存储系统中的数据存储的罐。 多个罐中的每一个可以具有配置成用于单处理器模式并具有内部节点标识符以识别处理器和外部节点标识符的处理器，以识别用于镜像缓存数据的另一个处理器。 缓存数据的镜像可以通过经由PtP互连的非相干事务的通信来执行，其中PtP互连是根据高速缓存一致性协议。 描述和要求保护其他实施例。

    INTERFACING BETWEEN DIFFERING VOLTAGE LEVEL REQUIREMENTS IN AN INTEGRATED CIRCUIT SYSTEM
    102.
    发明申请
    INTERFACING BETWEEN DIFFERING VOLTAGE LEVEL REQUIREMENTS IN AN INTEGRATED CIRCUIT SYSTEM 有权
    集成电路系统中不同电压等级要求之间的接口

    公开(公告)号：US20110102045A1

    公开(公告)日：2011-05-05

    申请号：US12610276

    申请日：2009-10-31

    Applicant: PANKAJ KUMAR ,  Pramod Elamannu Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande ,  John Kriz

    Inventor： PANKAJ KUMAR ,  Pramod Elamannu Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande ,  John Kriz

    IPC: H03L5/00

    CPC classification number: H03K17/693 ,  H03K19/00315 ,  H03K19/007

    Abstract: A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of an IO receiver, and controllably generating a second bias voltage from an external voltage supplied through an IO pad to be within the upper tolerable limit of the operating voltage of the IO receiver. The method also includes deriving an output voltage from the first bias voltage during a normal condition and a tolerant condition, and deriving the output voltage from the second bias voltage during a failsafe condition. The tolerant condition is a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage, and the failsafe condition is a mode of operation where the supply voltage is zero.

    Abstract translation: 一种方法包括可控制地从电源电压产生第一偏置电压，使其在IO接收器的工作电压的上限允许极限内，并且可控制地从通过IO焊盘提供的外部电压产生第二偏置电压以在上部 IO接收器的工作电压允许限制。 该方法还包括在正常条件和容限条件期间从第一偏置电压导出输出电压，以及在故障安全状态期间从第二偏置电压导出输出电压。 容许条件是通过IO垫提供的外部电压从零变化到高于电源电压的值的操作模式，并且故障保护条件是电源电压为零的操作模式。

    I/O buffer with low voltage semiconductor devices
    103.
    发明授权
    I/O buffer with low voltage semiconductor devices 失效
    具有低电压半导体器件的I / O缓冲器

    公开(公告)号：US07936209B2

    公开(公告)日：2011-05-03

    申请号：US12428556

    申请日：2009-04-23

    Applicant: Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

    Inventor： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

    IPC: G05F1/10 ,  G05F3/02

    CPC classification number: H03K17/0822 ,  H03K19/018528

    Abstract: Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

    Abstract translation: 所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。 第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。 第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。 从缓冲器的工作电压产生第一和第二偏置电压。 从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压 缓冲。 第三和第四偏置电压分别提供给第一和第二过压保护电路。

    PROCESSING OUT OF ORDER TRANSACTIONS FOR MIRRORED SUBSYSTEMS
    104.
    发明申请
    PROCESSING OUT OF ORDER TRANSACTIONS FOR MIRRORED SUBSYSTEMS 有权
    处理用于镜像子系统的订单交易

    公开(公告)号：US20100332756A1

    公开(公告)日：2010-12-30

    申请号：US12495676

    申请日：2009-06-30

    Applicant: Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

    Inventor： Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

    IPC: G06F12/08 ,  G06F1/30

    CPC classification number: G06F11/1666 ,  G06F11/20 ,  G06F2201/82

    Abstract: Methods and apparatus relating to processing out of order transactions for mirrored subsystems are described. In one embodiment, a device (that is mirroring data from another device) includes a cache to track out of order write operations prior to writing the data from the write operations to memory. A register may be used to track the state of the cache and cause acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Other embodiments are also disclosed.

    Abstract translation: 描述与处理镜像子系统的乱序事务相关的方法和装置。 在一个实施例中，在将写入操作的数据写入存储器之前，设备（即来自另一个设备的数据镜像）包括高速缓存以跟踪不合格的写入操作。 一旦由寄存器在选择点记录的所有高速缓存条目被清空或以其它方式被无效，则可以使用寄存器来跟踪高速缓存的状态并导致将数据承诺的确认。 还公开了其他实施例。

    Failsafe and tolerant driver architecture and method
    105.
    发明授权
    Failsafe and tolerant driver architecture and method 有权
    故障安全和容忍驱动程序架构和方法

    公开(公告)号：US07834653B1

    公开(公告)日：2010-11-16

    申请号：US12610275

    申请日：2009-10-31

    Applicant: Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande

    Inventor： Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande

    IPC: H03K19/007

    CPC classification number: H03K19/00315 ,  H03K17/08104 ,  H03K19/007

    Abstract: A method includes controllably utilizing a control signal generated by an Input/Output (IO) core to isolate a current path from an external voltage supplied through an IO pad to a supply voltage by transmitting a same voltage at an input terminal of a transistor, configured to be part of a number of cascaded transistors of an IO driver of an interface circuit, to an output terminal thereof during a failsafe mode of operation and a tolerant mode of operation. The method also includes feeding back an appropriate voltage to a floating node created by the isolation of the current path, and controlling a voltage across each transistor of the number of cascaded transistors to be within an upper tolerable limit thereof through an application of a gate voltage to each transistor derived from the supply voltage or the external voltage supplied through the IO pad.

    Abstract translation: 一种方法包括可控地利用由输入/输出（IO）芯产生的控制信号，以将电流路径与通过IO垫提供的外部电压隔离成电源电压，通过在晶体管的输入端发送相同的电压，配置 作为接口电路的IO驱动器的多个级联晶体管的一部分，在故障安全操作模式和容限操作模式期间连接到其输出端子。 该方法还包括将适当的电压反馈到通过隔离电流路径而产生的浮动节点，并且通过施加栅极电压来控制级联晶体管数量的每个晶体管上的电压在其可容许的上限范围内 到源于通过IO焊盘提供的电源电压或外部电压的每个晶体管。

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