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101.发明申请公开(公告)号：US20200005872A1
公开(公告)日：2020-01-02
申请号：US16432369
申请日：2019-06-05
Inventor： Leonardo Valencia Rissetto , Elise Le Roux , Christophe Forel
Abstract: A method can be used for programming a group of memory cells of a non-volatile memory device in a programming window that has a duration longer than a programming duration of a memory cell. The programming window is subdivided into a number of time intervals. A programming profile that was determined by simulation while taking into account a reference criterion is retrieved. The programming profile includes, for each time interval, a maximum number of memory cells that can be triggered for programming within each time interval. The memory device is programmed in the programming window, interval-wise, using the programming profile.
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公开(公告)号：US10423179B2
公开(公告)日：2019-09-24
申请号：US16381541
申请日：2019-04-11
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
IPC: H02J7/00 , G05F1/59 , H03F3/45 , H02J7/02 , G05F1/56 , H01R24/60 , H02J7/06 , G05F1/569 , H01R107/00 , H02J7/10
Abstract: A low dropout voltage regulator unit includes an error amplifier and a power stage having an output terminal that is looped back onto the error amplifier and is capable of delivering an output current to a load. The unit includes multiple main supply inputs that are intended to potentially receive, respectively, multiple different supply voltages. The power stage includes multiple power paths that are connected, respectively, between the main supply inputs and the output terminal, are individually selectable and each comprise an output transistor. The unit also includes a selector circuit connected to the main supply inputs and configured to select one of the power paths according to a selection criterion. The error amplifier includes an output stage configured to selectively control the output transistor of the selected power path.
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公开(公告)号：US10236842B2
公开(公告)日：2019-03-19
申请号：US15393485
申请日：2016-12-29
Inventor： Vratislav Michal , Michel Ayraud
Abstract: A circuit includes an amplifier having a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential. The circuit further includes a first impedance element coupled between a first input terminal of the amplifier and a first output terminal of the amplifier. The circuit additionally includes a second impedance element coupled between the first input terminal and the reference potential. The amplifier is configured to output a first voltage at a second output terminal of the amplifier in response to the supply voltage being greater than an output voltage at the first output terminal of the amplifier. The amplifier is further configured to output a second voltage at the second output terminal of the amplifier in response to the supply voltage being less than the output voltage at the first output terminal of the amplifier.
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公开(公告)号：US20180367171A1
公开(公告)日：2018-12-20
申请号：US16003623
申请日：2018-06-08
Applicant: STMicroelectronics (Alps) SAS
Inventor： Herve JACOB
IPC: H04B1/04
CPC classification number: H04B1/04 , H03F1/223 , H03F1/3247 , H03F3/195 , H03F3/245 , H03F3/45376 , H03F2200/204 , H03F2200/207 , H03F2200/534 , H03F2200/537 , H03F2200/555 , H03F2203/45394 , H03F2203/45544 , H03F2203/45548 , H03F2203/45594 , H03F2203/45604 , H04B2001/0425
Abstract: A transmission chain receives an incident signal to be transmitted having a first power and a first bandwidth. A first modulator frequency shifts a first signal derived from the incident signal to generate a first shifted signal at a modulation output. A power amplifier coupled to the modulation output amplifies an intermediate signal to generate an amplified output signal. A predistortion-signal-generating circuit generates, from the incident signal and from the amplified output signal in a second bandwidth that is larger than the first bandwidth, a predistortion signal having a second power lower than the first power. A second modulator frequency shifts a second signal derived from the predistortion signal to generate a second shifted signal for combination with the first shifted signal at said modulation output to produce the intermediate signal.
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105.发明申请公开(公告)号：US20180309187A1
公开(公告)日：2018-10-25
申请号：US16017611
申请日：2018-06-25
Inventor： David Auchere , Laurent Marechal , Yvon Imbs , Laurent Schwarz
IPC: H01Q1/22 , H01L23/31 , H01L21/56 , H01L23/498 , H01L21/48 , H01L23/66 , H01L21/3105
Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.
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Patent Agency Ranking
公开(公告)号：US20180270762A1
公开(公告)日：2018-09-20
申请号：US15692012
申请日：2017-08-31
Inventor： Michel Ayraud , Serge Ramet , Philippe Level
CPC classification number: H04W52/0274 , H03B5/1212 , H03B5/1278 , H03B21/025 , H03D7/166 , H03G3/3052 , H04B1/16 , H04B17/327 , Y02D70/00
Abstract: A local oscillator device includes an oscillator module including a first inductive element and a capacitive element coupled in parallel with the inductive element. A frequency divider is coupled to the oscillator module for delivering a local oscillator signal. The local oscillator device includes an autotransformer including the first inductive element and two second inductive elements respectively coupled to the terminals of the first inductive element and to two output terminals of the autotransformer, the output terminals being further coupled to input terminals of the frequency divider.
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公开(公告)号：US10067200B2
公开(公告)日：2018-09-04
申请号：US15076955
申请日：2016-03-22
Applicant: STMicroelectronics (Alps) SAS
Inventor： Bruno Leduc , Pascal Bernon , Stephane Clin
Abstract: A circuit includes, in series between a first terminal and a second terminal of application of a power supply voltage, and first and second branches. The first branch includes a first transistor and a first current source coupled to the first transistor. The second branch includes a resistive element, a second transistor coupled to the resistive element and forming a current mirror with the first transistor and a second current source coupled to the second transistor. The resistive element conditions a threshold of detection of a variation of the power supply voltage.
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公开(公告)号：US20180239384A1
公开(公告)日：2018-08-23
申请号：US15693214
申请日：2017-08-31
Inventor： Serge Ramet , Sandrine Nicolas , Danika Perrin , Cedric Rechatin
CPC classification number: G05F3/262 , G05F1/46 , H03F3/16 , H03F3/195 , H03F2200/294
Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
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公开(公告)号：US09933797B1
公开(公告)日：2018-04-03
申请号：US15495504
申请日：2017-04-24
Applicant: STMicroelectronics (Alps) SAS
Inventor： Frederic Lebon
Abstract: An integrated electronic device includes a core having a first terminal and a second terminal. The core includes a first branch with a first diode-connected bipolar transistor coupled in series to a first resistor between the first terminal and a reference terminal intended to be supplied with a reference voltage, and a second branch with a second diode-connected bipolar transistor coupled between the second terminal and the reference terminal. The second diode-connected bipolar transistor has a current density higher than the first diode-connected bipolar transistor. The core also includes a first resistive network coupled between a base of the first diode-connected bipolar transistor and the reference terminal. An equalizer is configured to equalize potentials of the first terminal and of the second terminal and a voltage generator is coupled to the first and second terminals of the core and configured to generate the bandgap voltage.
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公开(公告)号：US09892877B2
公开(公告)日：2018-02-13
申请号：US14657991
申请日：2015-03-13
Applicant: STMicroelectronics (Alps) SAS
Inventor： Vratislav Michal , Denis Cottin
CPC classification number: H01H47/00 , H03K17/167 , H03K17/30 , H03K2017/307 , Y10T307/76
Abstract: A circuit including: a plurality of first switches connected in parallel between a first terminal and a second terminal; and a control circuit capable of implementing the following steps at each period of a clock signal: comparing the voltage between the first and second terminals with a reference voltage; if the voltage between the first and second terminals is greater than the reference voltage, turning on one of the first switches without modifying the state of the other switches; and if the voltage between the first and second terminals is smaller than the reference voltage, turning off one of the first switches without modifying the state of the other switches.
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