公开(公告)号：US08081723B1

公开(公告)日：2011-12-20

申请号：US12082343

申请日：2008-04-09

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran

IPC分类号： H04L7/00

CPC分类号： H04L7/048 ,  H04L1/205 ,  H04L7/033

摘要： Methods and apparatus for determining at least part of the width of the eye of a high-speed serial data signal use clock and data recovery circuitry operating on that signal to produce a first clock signal having a first phase relationship to the data signal. The first clock signal is used to produce a second clock signal whose phase can be controllably shifted relative to the first phase. The second clock signal is used to sample the data signal with different amounts of phase shift, e.g., until error checking circuitry detects that data errors in the resulting sample exceed an acceptable threshold for such errors. The amount(s) of phase shift that caused exceeding the threshold can be used as a basis for a measurement of eye width.

摘要翻译： 用于确定高速串行数据信号的眼睛的至少部分宽度的方法和装置使用在该信号上操作的时钟和数据恢复电路，以产生与数据信号具有第一相位关系的第一时钟信号。 第一时钟信号用于产生第二时钟信号，其相位可相对于第一相位被可控地偏移。 第二时钟信号用于以不同量的相移对数据信号进行采样，例如直到错误检查电路检测到所得样本中的数据错误超过这种错误的可接受的阈值。 引起超过阈值的相移量可用作测量眼睛宽度的基础。

公开(公告)号：US20110264803A1

公开(公告)日：2011-10-27

申请号：US12921786

申请日：2008-03-13

申请人： John Yuen ,  Philip Steele ,  David Cauz ,  Wilson Wong

发明人： John Yuen ,  Philip Steele ,  David Cauz ,  Wilson Wong

IPC分类号： G06F15/173

CPC分类号： H04L41/0893 ,  H04L12/14 ,  H04L12/1403 ,  H04L12/1485 ,  H04L41/0806 ,  H04W28/16

摘要： A configurator is provided that connects with various disparate elements in a telecommunication system. The configurator is adapted to receive a traffic plan that has a plurality of different aspects that are implemented across the disparate elements. The configurator is adapted to generate processing schemas and/or databases that can be used by the disparate elements in order to implement the traffic plan.

摘要翻译： 提供了一种与电信系统中的各种不同的元件连接的配置器。 配置器适于接收具有跨不同元素实现的多个不同方面的流量计划。 配置器适于生成可由不同元件使用以便实现流量计划的处理模式和/或数据库。

公开(公告)号：US20110234331A1

公开(公告)日：2011-09-29

申请号：US12748261

申请日：2010-03-26

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

IPC分类号： H03B5/12 ,  H01F5/00

CPC分类号： H03B5/1212 ,  H01F2021/125 ,  H01F2027/2809 ,  H01L2924/0002 ,  H03B5/1243 ,  H03B5/1268 ,  H01L2924/00

摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

摘要翻译： 提供具有锁相环的集成电路。 锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。 压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。 多个电感器中选择的一个可以主动地连接到振荡器电路。 压控振荡器可以具有多个振荡器电路。 每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。 每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。 所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

公开(公告)号：US07996749B2

公开(公告)日：2011-08-09

申请号：US11773234

申请日：2007-07-03

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H03M13/03

CPC分类号： H04L25/45

摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

摘要翻译： 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

公开(公告)号：US20110188564A1

公开(公告)日：2011-08-04

申请号：US13079420

申请日：2011-04-04

申请人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

发明人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

IPC分类号： H03K5/125 ,  H03K5/19

CPC分类号： H04L25/03885

摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

公开(公告)号：US07898313B1

公开(公告)日：2011-03-01

申请号：US12723450

申请日：2010-03-12

申请人： Tin H. Lai ,  Wilson Wong

发明人： Tin H. Lai ,  Wilson Wong

IPC分类号： H03F3/45 ,  H03L5/00

CPC分类号： H03F3/45475 ,  H03F3/45192 ,  H03F3/45744 ,  H03F3/45968 ,  H03F2200/321 ,  H03F2203/45212 ,  H03F2203/45646 ,  H03F2203/45678 ,  H03F2203/45681 ,  H03F2203/45726

摘要： Techniques and circuitry are provided for programmably controlling signal offsets in integrated circuitry. In one embodiment, an integrated circuit includes a signal offset cancellation circuit that is programmably selected to control the offset of signals on either one input/output or another input/output of an amplifier circuit. In one embodiment, a logic circuit is used to selectively couple a bank of current sources to one input/output or another input/output of a differential amplifier through a switching circuit. The bank of current sources may employed to control the signal offset on either input/output, or may be decoupled from all of the inputs/outputs when signal offset cancellation is not required.

摘要翻译： 提供技术和电路用于可编程地控制集成电路中的信号偏移。 在一个实施例中，集成电路包括可编程地选择以控制放大器电路的一个输入/输出或另一个输入/输出上的信号的偏移的信号偏移消除电路。 在一个实施例中，逻辑电路用于通过开关电路将一组电流源选择性地耦合到差分放大器的一个输入/输出或另一个输入/输出。 可以采用电流源的组来控制输入/输出上的信号偏移，或者当不需要信号偏移消除时可以与所有的输入/输出去耦。

公开(公告)号：US07782935B1

公开(公告)日：2010-08-24

申请号：US11514490

申请日：2006-08-31

申请人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

发明人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

IPC分类号： H03H7/30

CPC分类号： H03H11/26 ,  H04L25/03878 ,  H04L2025/0349

摘要： Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1/n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.

摘要翻译： 提出了用于向高数据速率信号提供均衡的方法和电路，包括判决反馈均衡（DFE）。 半速率延迟链电路使用以输入信号数据速率的一小部分工作的两个或多个延迟链电路产生输入信号的延迟采样。 可以使用以输入信号数据速率的一半工作的两个延迟链电路。 更一般地，可以使用以1 / n输入信号数据速率工作的n个延迟链电路。 多路复用器电路组合延迟链电路的输出以产生包括输入信号数据速率的输入信号样本的输出信号。 重复路径DFE电路包括用于提供DFE均衡的两个路径，同时减少DFE电路之前的电路上的DFE电路的负载。 第一路径产生DFE信号的延迟采样，而第二路径产生来自延迟采样的DFE输出信号。

公开(公告)号：US07750674B2

公开(公告)日：2010-07-06

申请号：US12214466

申请日：2008-06-18

申请人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Richard G. Cliff

发明人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Richard G. Cliff

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/17784

摘要： High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.

摘要翻译： 可编程逻辑器件集成电路（“PLD”）上的高速串行接口或收发器电路包括允许PLD满足广泛可能的用户需求或应用的功能。 该范围包括高性能应用和PLD降低功耗很重要的应用。 在后一种情况下，可以使用任何一种或多种各种特征来帮助降低功耗。

公开(公告)号：US07702011B2

公开(公告)日：2010-04-20

申请号：US11361192

申请日：2006-02-23

申请人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

发明人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

IPC分类号： H03H7/30

CPC分类号： H04L1/243 ,  H04L25/03878

摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.

摘要翻译： 用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。 其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。 例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。 接收器电路的控制的各个方面可以是可编程的。

公开(公告)号：US20100058099A1

公开(公告)日：2010-03-04

申请号：US12576507

申请日：2009-10-09

申请人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC分类号： G06F1/04 ,  G06F1/12

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。