公开(公告)号：US20250087296A1

公开(公告)日：2025-03-13

申请号：US18243441

申请日：2023-09-07

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Khushal Gelda ,  Ramesh Manohar ,  Teresa Louise Mclaurin ,  Prashant Mohan Kulkarni

IPC: G11C29/00 ,  G11C29/18 ,  G11C29/44

Abstract: Various implementations described herein are directed to a device having a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells. Also, the device may have control circuitry configured to access and repair a first bitcell in the first row slice with a first row address and a second bitcell in the second row slice with a second row address that is different than the first row address.

公开(公告)号：US12164855B2

公开(公告)日：2024-12-10

申请号：US17209903

申请日：2021-03-23

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Andy Wangkun Chen

IPC: G06F30/3953

Abstract: Various implementations described herein are directed to a method for identifying pre-routed metal lines in a higher layer of a multi-layered structure. The method may recognize gaps in the pre-routed metal lines of the higher layer, and also, the method may automatically fill the gaps with conductive stubs to modify the pre-routed metal lines in the higher layer as a continuous metal line with an extended length.

公开(公告)号：US12087357B2

公开(公告)日：2024-09-10

申请号：US17844551

申请日：2022-06-20

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen ,  Arjun Singh ,  Ayush Kulshrestha

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein are directed to a device having memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port. The device may have read-write circuitry coupled to the read-write port, wherein the read-write circuitry has write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle.

公开(公告)号：US12066855B2

公开(公告)日：2024-08-20

申请号：US18091719

申请日：2022-12-30

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Akash Bangalore Srinivasa ,  Munish Kumar ,  Khushal Gelda ,  Akshay Kumar

IPC: G06F1/00 ,  G06F1/06 ,  G06F1/10 ,  G06F11/30

CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F11/3062

Abstract: Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.

公开(公告)号：US20240233814A9

公开(公告)日：2024-07-11

申请号：US17971226

申请日：2022-10-21

Applicant: Arm Limited

Inventor： Vianney Antoine Choserot ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.

公开(公告)号：US11900995B2

公开(公告)日：2024-02-13

申请号：US17223950

申请日：2021-04-06

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Ayush Kulshrestha ,  Munish Kumar

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412

CPC classification number: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.

公开(公告)号：US11862271B2

公开(公告)日：2024-01-02

申请号：US16418833

申请日：2019-05-21

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yannis Jallamion-Grive ,  Cyrille Nicolas Dray

IPC: G11C29/00 ,  G11C29/42 ,  G06F11/27 ,  G06F11/10 ,  G11C29/34 ,  G11C29/02 ,  G11C29/18

CPC classification number: G11C29/42 ,  G06F11/102 ,  G06F11/106 ,  G06F11/27 ,  G11C29/025 ,  G11C29/34 ,  G11C29/781 ,  G11C29/802 ,  G11C2029/1802

Abstract: Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.

公开(公告)号：US20230410896A1

公开(公告)日：2023-12-21

申请号：US17844551

申请日：2022-06-20

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen ,  Arjun Singh ,  Ayush Kulshrestha

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein are directed to a device having memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port. The device may have read-write circuitry coupled to the read-write port, wherein the read-write circuitry has write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle.

公开(公告)号：US11837543B2

公开(公告)日：2023-12-05

申请号：US17006695

申请日：2020-08-28

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: H01L23/528 ,  H01L27/06

CPC classification number: H01L23/5286 ,  H01L27/0688

Abstract: Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.

公开(公告)号：US20230178538A1

公开(公告)日：2023-06-08

申请号：US18103313

申请日：2023-01-30

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha

IPC: H01L27/02 ,  G06F30/31 ,  H01L21/768 ,  H01L23/535 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L27/0207 ,  G06F30/31 ,  H01L21/76898 ,  H01L23/535 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06544

Abstract: According to one implementation of the present disclosure, a method includes fabricating a memory macro unit; forming a through silicon via (TSV); and bonding the TSV at least partially through the fabricated memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.