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公开(公告)号：US06918072B2
公开(公告)日：2005-07-12
申请号：US09864682
申请日：2001-05-24
IPC分类号： G01R31/28 , G11C11/401 , G11C11/413 , G11C16/02 , G11C29/00 , G11C29/12 , G11C29/44
摘要： Circuitry is provided to allow early switching of input signals from a first configuration directed to blow a first anti-fuse to a second configuration directed to blow a second anti-fuse, yet still allow complete blowing of the first anti-fuse. Such circuitry may be applied to methods of repairing a memory device after testing. Data concerning available repair cells may be stored in at least one on-chip redundancy register.
摘要翻译： 提供电路以允许将来自第一配置的输入信号的早期切换引导为将第一反熔丝吹向第二配置以引导第二反熔丝，但仍允许第一反熔丝完全吹动。 这样的电路可以应用于在测试之后修复存储器件的方法。 关于可用修复单元的数据可以存储在至少一个片上冗余寄存器中。
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公开(公告)号：US06904552B2
公开(公告)日：2005-06-07
申请号：US09810366
申请日：2001-03-15
申请人： Timothy B. Cowles
发明人： Timothy B. Cowles
IPC分类号： G01R31/28 , G11C11/401 , G11C11/413 , G11C16/02 , G11C29/00 , G11C29/12 , G11C29/44
摘要： A preferred exemplary embodiment of the current invention concerns a memory testing process, wherein circuitry is provided on a chip to allow on-chip comparison of stored data and expected data. The on-chip comparison allows the tester to transmit in a parallel manner the expected data to a plurality of chips. In a preferred embodiment, at most one address—and only the column address—corresponding to a failed memory cell is stored in an on-chip register at one time, with each earlier failed addresses being cleared from the register in favor of a subsequent failed address. Another bit—the “fail flag” bit—is stored in the register to indicate that a failure has occurred. If the fail flag is present in a chip, that chip is repaired by electrically associating the column address with redundant memory cells rather than the original memory cells. Subsequently, the chip's register may be cleared and testing may continue. It is preferred that the register and related logic circuitry be configured to avoid storing an address that is already associated with a redundant cell, even though that redundant cell has failed.
摘要翻译： 本发明的优选示例性实施例涉及存储器测试过程，其中在芯片上提供电路以允许对存储的数据进行片上比较和预期数据。 片上比较允许测试者以平行的方式将预期数据传输到多个芯片。 在优选实施例中，最多一个地址 - 并且仅一个对应于故障存储器单元的列地址一次存储在片上寄存器中，其中每个较早的失败地址从寄存器中清除以有利于随后的故障 地址。 另一位 - “失败标志”位存储在寄存器中，表示发生故障。 如果芯片中存在故障标志，则通过将列地址与冗余存储器单元而不是原始存储器单元电连接来修复该芯片。 随后，芯片的寄存器可能会被清除，测试可能会继续。 优选地，寄存器和相关逻辑电路被配置为避免存储已经与冗余单元相关联的地址，即使该冗余单元已经失败。
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公开(公告)号：US06864725B2
公开(公告)日：2005-03-08
申请号：US10161601
申请日：2002-06-05
申请人： Timothy B. Cowles , Steve Casper
发明人： Timothy B. Cowles , Steve Casper
IPC分类号： H03K19/0185 , H03B1/00
CPC分类号： H03K19/018528
摘要： A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages.
摘要翻译： 公开了一种低电流输入缓冲器。 缓冲器使用自偏置N和P通道差分对，其输出端连接在一起。 自偏置有助于减少电流消耗。 N沟道和P沟道差分对的组合导致了宽范围的参考电压和电源电压的对称性。
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公开(公告)号：US06809974B2
公开(公告)日：2004-10-26
申请号：US10231513
申请日：2002-08-29
IPC分类号： G11C700
摘要： A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.
摘要翻译： 提供了一种在测试模式期间监视存储器件中的延迟锁定环（DLL）的特性的方法。 DLL根据外部时钟信号产生内部时钟信号。 外部和内部时钟信号通常是同步的。 DLL不断响应存储器件的工作状态的变化，以保持外部和内部时钟同步。 该方法涉及防止DLL响应于在测试模式期间存储器件的电源电压变化的操作条件的改变。
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公开(公告)号：US06693835B2
公开(公告)日：2004-02-17
申请号：US10126424
申请日：2002-04-19
IPC分类号： G11C700
CPC分类号： G11C11/409 , G11C7/1018 , G11C7/1072 , G11C7/22
摘要： A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.
摘要翻译： 一种用于通过在读脉冲串期间允许IO线的上拉结束而在行地址锁存和列地址锁存（tRCD）之间改变时间的方法和装置，而不是等待下一个时钟信号 的READ操作。 在活动命令期间设置锁存器，以便设置节点电压，其允许IO上拉信号在列访问信号的触发时结束。 本发明允许改进tRCD参数，并且允许数字线对在读取数据突发的第一位之前与IO线分离而不需要线共享。 结果是在READ序列期间更精确和无错误地读取第一位数据。
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公开(公告)号：US06574164B2
公开(公告)日：2003-06-03
申请号：US10126412
申请日：2002-04-19
IPC分类号： G11C800
CPC分类号： G11C11/409 , G11C7/1018 , G11C7/1072 , G11C7/22
摘要： A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.
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107.发明授权公开(公告)号：US06556497B2
公开(公告)日：2003-04-29
申请号：US10043462
申请日：2002-01-10
IPC分类号： G11C700
CPC分类号： G11C7/1045 , G11C7/1072 , G11C11/406
摘要： A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the half density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode. The SDRAM also includes circuitry for remapping one of the row address bits for use as a column address bit in the half density mode so that the SDRAM can interface with system adapted for conventional dual mode SDRAMs.
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公开(公告)号：US06525982B1
公开(公告)日：2003-02-25
申请号：US09954600
申请日：2001-09-11
申请人： Timothy B. Cowles
发明人： Timothy B. Cowles
IPC分类号： G11C700
CPC分类号： G11C17/18 , G11C17/16 , G11C2207/105
摘要： As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.
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109.发明授权公开(公告)号：US06310819B1
公开(公告)日：2001-10-30
申请号：US09703496
申请日：2000-10-31
申请人： Timothy B. Cowles , Jeffrey P. Wright , Hua Zheng
发明人： Timothy B. Cowles , Jeffrey P. Wright , Hua Zheng
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.
摘要翻译： 只要在生成自动刷新命令之后的预定等待时间段内，自刷新解码器产生自刷新命令，只要时钟使能信号变为低电平即可。 结果，即使将与自刷新命令相区别的自动刷新命令的时钟使能控制信号被过度延迟超过对应于自刷新命令和自刷新命令的其他控制信号，SDRAM也能够进入自刷新模式 。 自刷新解码器包括预先加载等待时间值的计数器，并且响应于自动刷新命令而减小到终端计数以终止等待时间。 只要终端计数未达到，计数器的输出被解码以提供使能信号。 只要存在使能信号，响应于接收到时钟使能信号而产生自刷新命令。
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公开(公告)号：US06253340B1
公开(公告)日：2001-06-26
申请号：US09093967
申请日：1998-06-08
IPC分类号： G11C2900
CPC分类号： G01R31/318505
摘要： Systems, methods and apparatus for accessing integrated circuits, such as semiconductor memories and particularly in testing, by reducing the number of clock cycles required to apply sequences of command and address signals to a m-dimensional structure of such integrated circuit, such as a memory array. The system, methods and apparatus comprise structure and steps by which commands are issued responsive to external controls signals and commands are generated independent of such signals, such commands being communicated internal to the integrated circuit via separate data paths.
摘要翻译： 通过减少将命令和地址信号序列应用到诸如存储器的集成电路的m维结构所需的时钟周期的数量来访问诸如半导体存储器，特别是在测试中的集成电路的系统，方法和装置 数组。 系统，方法和装置包括响应外部控制信号发出命令的结构和步骤，独立于这种信号产生命令，这些命令通过单独的数据路径在集成电路内部传送。
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