Abstract:
A method and apparatus to provide a hierarchical timing model with crosstalk consideration is provided. In one embodiment, the method comprises performing block level analysis of a circuit, in one or a plurality of iterations, and storing per iteration data. The method further comprises, in one embodiment, utilizing the per iteration data in performing top level analysis of the circuit.
Abstract:
An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.
Abstract:
The invention is directed to an optical device comprising refractive optical structures, wherein the refractive structures are characterized by a change in refractive index, exhibit little or no scattering loss, and exhibit no significant differences in the Raman spectrum with respect to the non-irradiated optical, polymeric material.
Abstract:
This invention relates to a desorption/ionization source operated under ambient conditions for direct analysis of solid or liquid samples on a surface. The source comprises of a laser desorption system and a UV/electrospray combined ionization system. The source is suitable for simultaneously ionizing samples with different polarity in a complex mixture. At the same time, the compact design of the source with multiple channels can maintain the level of local concentration of the analyte ions inside the source for higher efficiency of sample ionization and introduction.
Abstract:
A method and apparatus to provide a hierarchical timing model with crosstalk consideration is provided. In one embodiment, the method comprises performing block level analysis of a circuit, in one or a plurality of iterations, and storing per iteration data. The method further comprises, in one embodiment, utilizing the per iteration data in performing top level analysis of the circuit.
Abstract:
An interactive user interface (UI) to manage searching of data is disclosed. The UI includes a first display panel configured to display a parent context view and a child context view thereon and a second display panel configured to display a diagram of an enlarged portion of the child context view.
Abstract:
Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to analyze an electrical characteristic of a logic gate electrically coupled to an output network in a stage. In particular, during the analysis, the effective capacitance of an output network coupled to a logic gate is approximated as a function of a total resistance of the output network, a total capacitance of the output network, and a geometric parameter of the output network. Using the effective capacitance and other parameters, such as a slew rate of an electrical signal applied to an input of the logic gate, an electrical characteristic of the logic gate, such as an input capacitance, is determined.
Abstract:
One embodiment of the present invention provides systems and techniques for generating a transistor-level description of a subcircuit. A user may want to simulate a subcircuit in a circuit using a transistor-level simulator, and one or more cells in the subcircuit may need to be sensitized so that the cells are in a desired state when the subcircuit is simulated. An embodiment modifies the subcircuit by inserting analog switches in front of the cells that need to be sensitized, so that the analog switches can be used to apply a sensitization sequence to the cells during the transistor-level simulation. The embodiment can then generate a transistor-level description of the modified subcircuit. Next, the transistor-level description of the subcircuit can be stored, thereby enabling the transistor-level simulator to simulate the subcircuit.
Abstract:
A source container for use in a computer system executing problem determination tools in an integrated environment across a computer network, the source container comprising a list of pathways to a plurality of source files and module objects. A software development may create the source container independently or within the front end of a problem determination tool. The front end of the problem determination tools sends the source container to its engine, and only source files and module objects having a pathway in the source container are analyzed within the engine of the problem determination tool. Furthermore, the results of the analysis of only those source files and module objects having a pathway in the source container are returned to the front end of the problem determination tool for viewing by the software developer. The front ends of the tools of the integrated development environment, the source files, the module objects, the engines of the tools, and different tools may all be located on different servers and/or clients across a computer network.
Abstract:
The invention is directed to an optical device comprising refractive optical structures, wherein the refractive structures are characterized by a change in refractive index, exhibit little or no scattering loss, and exhibit no significant differences in the Raman spectrum with respect to the non-irradiated optical, polymeric material.