公开(公告)号：US5446698A

公开(公告)日：1995-08-29

申请号：US268788

申请日：1994-06-30

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/808

Abstract: According to the present invention, defective element(s), such as a faulty local wordline, of an integrated circuit memory device may be selectively replaced with redundant element(s) in an efficient and flexible manner that does not require replacement of all elements associated with a master element of the memory device, thereby increasing the efficiency with which faulty elements of the memory device may be replaced. For a SRAM having a plurality of blocks, this is accomplished by combining defective block information as well as defective element information, such as bad row information, in the redundant global wordline control circuitry of the device. Then, the "normal" global wordline associated with a faulty local wordline is selectively disabled and a redundant global wordline is selectively enabled, upon detection of the address of the faulty local wordline. The normal global wordline can be enabled when the address corresponds to a non-faulty local wordline.

Abstract translation: 根据本发明，集成电路存储器件的有缺陷的元件（例如故障的局部字线）可以以有效且灵活的方式被选择性地替换为冗余元件，其不需要更换相关的所有元件 具有存储器件的主元件，从而提高可以替换存储器件的故障元件的效率。 对于具有多个块的SRAM，这通过将缺陷块信息以及诸如不良行信息的有缺陷的元素信息组合在设备的冗余全局字线控制电路中来实现。 然后，在检测到故障的本地字线的地址时，选择性地禁用与故障本地字线相关联的“正常”全局字线，并且选择性地使能冗余全局字线。 当地址对应于无故障的本地字线时，可以启用正常的全局字线。

公开(公告)号：US5424988A

公开(公告)日：1995-06-13

申请号：US954276

申请日：1992-09-30

Applicant: David C. McClure ,  James Brady

Inventor： David C. McClure ,  James Brady

IPC: G01R31/28 ,  G11C11/413 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  G11C29/50 ,  G11C7/00

CPC classification number: G11C29/34 ,  G11C29/50 ,  G11C11/41

Abstract: A method for stress testing a memory array in an integrated circuit. Control circuitry selects a plurality of row lines at one time. An overvoltage suitable for stressing the cells of the array is placed on the bit lines. Because a block of cells has been selected, the overvoltage is applied to all cells of the block. The block of cells selected may be either the entire memory array or a portion of the memory array. The selected rows remain selected for the duration of the stress test. Because the overvoltage is applied directly to selected cells, the full overvoltage will be used to stress the transistor gates for the entire test period. In this manner, latent defects within the memory array can be detected.

Abstract translation: 一种用于对集成电路中的存储器阵列进行应力测试的方法。 控制电路一次选择多行行。 适用于对阵列的单元进行加压的过电压放置在位线上。 因为已经选择了一个单元块，所以过电压被施加到该块的所有单元。 所选择的单元块可以是整个存储器阵列或存储器阵列的一部分。 所选行在压力测试期间保持选择。 因为过电压直接应用于所选择的单元，所以在整个测试周期中，将使用全过电压来施加晶体管栅极。 以这种方式，可以检测存储器阵列内的潜在缺陷。

公开(公告)号：US5355344A

公开(公告)日：1994-10-11

申请号：US975628

申请日：1992-11-13

Applicant: David C. McClure

Inventor： David C. McClure

IPC: H01L21/82 ,  G11C29/00 ,  G11C29/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10 ,  G11C7/00

CPC classification number: G11C29/76 ,  H01L27/0207

Abstract: Two addresses of an integrated circuit are selected to define a portion of the die which is functional and the portion of the die which will not be used. An input structure for addresses, which may be added to part of the electrostatic discharge (ESD) input structure of a pin, allows an address signal to be set to a predetermined logic level and to not be bonded out to the package. Additionally, another input structure allows the mapping of a signal pin to be changed. The function of a pin may need to be changed to accommodate a pinout for a different density device. This is useful when a die is put into a smaller density device package which has a pin out that does not accommodate the die. In this way, partially functional die that previously were discarded may be utilized, thereby recouping potential losses during manufacturing.

Abstract translation: 选择集成电路的两个地址以限定芯片的功能部分和不使用的芯片部分。 可以添加到引脚的静电放电（ESD）输入结构的一部分的地址的输入结构允许地址信号被设置为预定的逻辑电平并且不被结合到封装。 另外，另一输入结构允许映射要改变的信号引脚。 可能需要改变引脚的功能以适应不同密度器件的引脚排列。 当将管芯放入具有不能容纳管芯的销钉的较小密度的器件封装中时，这是有用的。 以这种方式，可以利用先前被丢弃的部分功能的模具，从而在制造过程中补偿潜在的损失。

公开(公告)号：US5349246A

公开(公告)日：1994-09-20

申请号：US995666

申请日：1992-12-21

Applicant: David C. McClure

Inventor： David C. McClure

IPC: H03K3/3565 ,  H03K17/16

CPC classification number: H03K3/3565

Abstract: An input buffer circuit is disclosed which has feedback hysteresis transistors having similar size characteristics as the drive transistors. The drive transistors are located in a first inverting CMOS stage, connected in conventional CMOS inverter fashion. The drains of the drive transistors are connected to the input of an inverter, the output of which drives the signal to elsewhere in the integrated circuit. A first hysteresis leg is provided, consisting of a plurality of p-channel transistors with their source/drain paths in series between the input of the inverter and a power supply voltage; the gate of at least one of the p-channel hysteresis transistors is coupled to the output of the inverter, and the gates of those of the hysteresis transistors that are not coupled to the inverter output are biased to ground. A second hysteresis leg of n-channel hysteresis transistors, similarly but complementarily configured, is provided between ground and the inverter input. The hysteresis transistors each have channel lengths substantially the same as the drive transistors, thus reducing the capacitive load at the output of the inverter and also ensuring good tracking over process variations; the channel widths of the hysteresis transistors may also be made sufficiently wide to avoid small width effects, and thus also provide improved tracking.

Abstract translation: 公开了具有与驱动晶体管相似尺寸特性的反馈滞后晶体管的输入缓冲电路。 驱动晶体管位于以常规CMOS反相器方式连接的第一反相CMOS级中。 驱动晶体管的漏极连接到逆变器的输入端，逆变器的输出将信号驱动到集成电路中的其他地方。 提供了第一滞后支路，其由多个p沟道晶体管组成，其源极/漏极路径串联在反相器的输入端和电源电压之间; p沟道磁滞晶体管中的至少一个的栅极耦合到反相器的输出，并且未耦合到反相器输出的滞环晶体管的栅极偏置于地。 类似地但互补配置的n沟道磁滞晶体管的第二滞后支路设置在地与逆变器输入端之间。 磁滞晶体管各自具有与驱动晶体管基本相同的沟道长度，因此降低了逆变器输出端的容性负载，并且还确保了对过程变化的良好跟踪; 滞后晶体管的通道宽度也可以被制成足够宽以避免小的宽度效应，因此也提供改进的跟踪。

公开(公告)号：US5265054A

公开(公告)日：1993-11-23

申请号：US627403

申请日：1990-12-14

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C29/04 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C29/84

Abstract: An integrated circuit memory is disclosed which includes redundant columns associated with a sub-array, and in which multiple input/output terminals are placed in communication with multiple columns in the sub-array in read and write cycles. The number of redundant columns per sub-array is less than the number of input/output terminals. A multiplexer connects the selected redundant column to a selected sense amplifier and write circuit for the input/output with which the replaced column was associated. The multiplexer includes pass gates connected to the bit lines of the redundant column, and fuses connected between each of the pass gates and each of the sense/write circuits selectable for the redundant column. Those of the fuses which are not associated with the selected input/output are opened, and the fuses associated with the selected input/output are left intact. Precharge transistors are connected to the fuse sides of the pass gates, for precharging each of the floating nodes after the pass gates are turned off. This precharging negates the effect of any charge which may be trapped on the fuse side of the pass gates for those lines where the fuses are opened, so that the access time for the next cycle will not be degraded.

公开(公告)号：US5206817A

公开(公告)日：1993-04-27

申请号：US600201

申请日：1990-10-18

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G06F5/12 ,  G01R29/027 ,  G06F5/10 ,  G06F7/02 ,  G06F13/38 ,  G11C7/00

CPC classification number: G06F5/12 ,  G01R29/0273 ,  G06F7/026 ,  G06F2205/126

Abstract: A first-in, first-out (FIFO) memory includes flag generation circuitry which utilizes a write clock counter and a read clock counter to provide the number of write clock pulses received since the previous write reset signal and the number of read clock pulses received by the FIFO since the previous read reset signal. Specific flag values are user-programmable and are stored electronically as binary numbers in registers. The connection between individual subtractor circuits and individual comparator circuits for making a difference comparison is performed by a program select decoder which utilizes the difference output of the subtractor circuit and the flag program value. False flag information is filtered by a bi-stable de-glitch circuit which includes a delay path to emulate operation of the counter, subtractor and comparator. The magnitude comparator is programmed one count away from the desired flag transition point. The filtered flag output is updated at the onset of each blanking interval, thus making it representative of the current state of the FIFO.

Abstract translation: 先进先出（FIFO）存储器包括标志产生电路，其利用写时钟计数器和读时钟计数器来提供从先前的写入复位信号和接收到的读取时钟脉冲的数量所接收的写入时钟脉冲的数量 由先前读取复位信号的FIFO。 特定的标志值是用户可编程的，并以电子方式存储在寄存器中作为二进制数字。 用于进行差分比较的各个减法器电路和各个比较器电路之间的连接由利用减法器电路的差分输出和标志程序值的程序选择解码器执行。 假标志信息由双稳态去毛刺电路滤波，该电路包括用于模拟计数器，减法器和比较器的操作的延迟路径。 幅度比较器被编程为远离所需标志转换点的一个计数。 在每个消隐间隔的开始处更新滤波的标志输出，从而使其代表FIFO的当前状态。

公开(公告)号：US5161159A

公开(公告)日：1992-11-03

申请号：US568968

申请日：1990-08-17

Applicant: David C. McClure ,  Thomas A. Coker

Inventor： David C. McClure ,  Thomas A. Coker

IPC: G06F11/22 ,  G01R31/317 ,  G11C29/14 ,  G11C29/46

CPC classification number: G11C29/46 ,  G01R31/31701

Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

公开(公告)号：US5072138A

公开(公告)日：1991-12-10

申请号：US570203

申请日：1990-08-17

Applicant: William C. Slemmer ,  Thomas A. Coker ,  David C. McClure

Inventor： William C. Slemmer ,  Thomas A. Coker ,  David C. McClure

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  G11C7/10 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  H01L21/66 ,  H01L27/10

CPC classification number: G11C29/46 ,  G01R31/31701 ,  G01R31/31719 ,  G11C7/1045

Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. In addition, sequential codes may be used for further security. Logic for evaluating both a sequence of codes received in parallel from a number of address terminals, and also a sequence of serial codes received at single address terminal, are disclosed. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

公开(公告)号：US5005158A

公开(公告)日：1991-04-02

申请号：US464219

申请日：1990-01-12

Applicant: David C. McClure ,  Mark A. Lysinger

Inventor： David C. McClure ,  Mark A. Lysinger

IPC: G11C8/04 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/86 ,  G11C8/04

Abstract: A fault tolerant sequential memory includes primary and redundant memory rows (or columns) and primary and redundant shift registers. The redundant memory rows (or columns) and redundant shift registers are formed at the end of the serial chain. Each shift register of each primary and redundant memory block is interconnected with an independent, separately programmable multiplexer logic circuit. Each multiplexer logic circuit includes an independently programmable repair buffer for logically bypassing a defective primary memory block and associated shift registers within the primary memory array. Each redundant memory block includes a multiplexer logic circuit having an independently programmable repair buffer for logically enabling a redundant memory block and shift register at the end of the serial chain. Consequently, a faulty memory block, including its shift register and memory row (or column) is bypassed and is effectively removed from the shifting sequence. The redundant memory block, including a redundant shift register and a redundant row (or column), is inserted at the end of the shift register chain by opening a programmable fuse element.

公开(公告)号：US08482964B2

公开(公告)日：2013-07-09

申请号：US12645039

申请日：2009-12-22

Applicant: Kevin K. Walsh ,  Paul F. Gerrish ,  Larry E. Tyler ,  Mark A. Lysinger ,  David C. McClure ,  Francois Jacquet

Inventor： Kevin K. Walsh ,  Paul F. Gerrish ,  Larry E. Tyler ,  Mark A. Lysinger ,  David C. McClure ,  Francois Jacquet

IPC: G11C11/00

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C11/417

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract translation: 具有串联连接在每个存储单元的相应位存储节点之间的两个电容器的SRAM。 存储单元的两个反相器由正电压和低电压供电。 两个电容器在公共节点处彼此连接。 泄漏电流发生器耦合到公共节点。 泄漏电流发生器向公共节点提供泄漏电流，以保持大约在高和低SRAM电源的电压之间的一半的电压。