公开(公告)号：US07827388B2

公开(公告)日：2010-11-02

申请号：US12044846

申请日：2008-03-07

申请人： John Wesley Ward, III ,  Minh Michelle Quy Pham ,  Ronald Nick Kalla ,  Balaram Sinharoy

发明人： John Wesley Ward, III ,  Minh Michelle Quy Pham ,  Ronald Nick Kalla ,  Balaram Sinharoy

IPC分类号： G06F9/40 ,  G06F9/42

CPC分类号： G06F9/4818 ,  G06F9/3851

摘要： Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between the threads according to some instruction interleave rule. However, upon the occurrence of some predefined event or circumstance in the processor related to a particular instruction thread, the base input processing priority of one or more instruction threads is adjusted to produce one more adjusted priority values. The instruction interleave rule is then enforced according to the adjusted priority value or values together with any base input processing priority values that have not been subject to adjustment.

摘要翻译： SMT处理器中的每个指令线程与软件分配的基本输入处理优先级相关联。 除非正在处理或要处理的指令发生一些预定义的事件或情况，否则各个线程的基本输入处理优先级用于根据某种指令交错规则来确定线程之间的交织频率。 然而，在与特定指令线程相关的处理器中发生某些预定义的事件或环境时，调整一个或多个指令线程的基本输入处理优先级以产生一个更多调整的优先级值。 然后根据调整后的优先级值或与未经调整的任何基本输入处理优先级值一起实施指令交错规则。

公开(公告)号：US20100250853A1

公开(公告)日：2010-09-30

申请号：US11482222

申请日：2006-07-07

申请人： Orran Y. Krieger ,  Balaram Sinharoy ,  Robert B. Tremaine ,  Robert W. Wisniewski

发明人： Orran Y. Krieger ,  Balaram Sinharoy ,  Robert B. Tremaine ,  Robert W. Wisniewski

IPC分类号： G06F12/10 ,  G06F12/08 ,  G06F13/24

CPC分类号： G06F12/1027 ,  G06F12/0862 ,  G06F2212/6028 ,  G06F2212/651 ,  G06F2212/654

摘要： A method and system for prefetching in computer system are provided. The method in one aspect includes using a prefetch engine to perform prefetch instructions and to translate unmapped data. Misses to address translations during the prefetch are handled and resolved. The method also includes storing the resolved translations in a respective cache translation table. A system for prefetching in one aspect includes a prefetch engine operable to receive instructions to prefetch data from the main memory. The prefetch engine is also operable to search cache address translation for prefetch data and perform address mapping translation, if the prefetch data is unmapped. The prefetch engine is further operable to prefetch the data and store the address mapping in one or more cache memory, if the data is unmapped.

摘要翻译： 提供了一种在计算机系统中预取的方法和系统。 该方法在一个方面包括使用预取引擎来执行预取指令并转换未映射的数据。 在预取期间解决翻译错误的处理和解决。 该方法还包括将分辨的翻译存储在相应的缓存转换表中。 用于在一个方面预取的系统包括预取引擎，其可操作以接收从主存储器预取数据的指令。 如果预取数据未被映射，则预取引擎还可用于搜索缓存地址转换以获取预取数据并执行地址映射转换。 如果数据未被映射，则预取引擎还可操作以预取数据并将地址映射存储在一个或多个高速缓冲存储器中。

公开(公告)号：US07765384B2

公开(公告)日：2010-07-27

申请号：US11736844

申请日：2007-04-18

申请人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

发明人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/384 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3861

摘要： A unified register rename mechanism for targets of different instruction types is provided in a microprocessor. The universal rename mechanism renames destinations of different instruction types using a single rename structure. Thus, an instruction that is updating a floating point register (FPR) can be renamed along with an instruction that is updating a general purpose register (GPR) or vector multimedia extensions (VMX) instructions register (VR) using the same rename structure because the number of architected states for GPR is the same as the number of architected states for FPR and VR. Each destination tag (DTAG) is assigned to one destination. A floating point instruction may be assigned to a DTAG, and then a fixed point instruction may be assigned to the next DTAG and so forth. With a universal rename mechanism, significant silicon and power can be saved by having only one rename structure for all instruction types.

摘要翻译： 在微处理器中提供了用于不同指令类型的目标的统一寄存器重命名机制。 通用重命名机制使用单个重命名结构重命名不同指令​​类型的目标。 因此，更新浮点寄存器（FPR）的指令可以与使用相同的重命名结构更新通用寄存器（GPR）或向量多媒体扩展（VMX）指令寄存器（VR））的指令一起重命名，因为 GPR的架构状态数量与FPR和VR的架构状态数量相同。 每个目的地标签（DTAG）被分配到一个目的地。 可将浮点指令分配给DTAG，然后将固定点指令分配给下一个DTAG等等。 使用通用重命名机制，可以通过为所有指令类型只有一个重命名结构来节省显着的硅和功率。

公开(公告)号：US20100153681A1

公开(公告)日：2010-06-17

申请号：US12336315

申请日：2008-12-16

申请人： Ravi K. Arimilli ,  Balaram Sinharoy

发明人： Ravi K. Arimilli ,  Balaram Sinharoy

IPC分类号： G06F9/34 ,  G06F12/02

CPC分类号： G06F9/383 ,  G06F9/30094 ,  G06F9/345

摘要： A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, an instruction sequencing unit that fetches instructions for execution by the at least one execution unit, and an address generation accelerator. The address generation accelerator, responsive to an initiation signal received from the instruction sequencing unit, computes and outputs first and second effective addresses of operands of an operation.

摘要翻译： 处理器包括执行指令的至少一个执行单元，耦合到所述至少一个执行单元的至少一个寄存器文件，其缓冲由所述至少一个执行单元访问的操作数，指令排序单元，其通过 所述至少一个执行单元和地址生成加速器。 地址产生加速器响应于从指令排序单元接收的发起信号，计算并输出操作的操作数的第一和第二有效地址。

公开(公告)号：US20100153648A1

公开(公告)日：2010-06-17

申请号：US12336350

申请日：2008-12-16

申请人： Ravi K. Arimilli ,  Balaram Sinharoy

发明人： Ravi K. Arimilli ,  Balaram Sinharoy

IPC分类号： G06F12/00

CPC分类号： G06F9/383 ,  G06F2212/6028

摘要： A processor has an associated memory hierarchy including a cache memory. The processor includes an instruction sequencing unit that fetches instructions for processing, an operand data structure including a plurality of entries corresponding to operands of operations to be performed by the processor, and a computation engine. A first entry among the plurality of entries in the operand data structure specifies a first caching policy for a first operand, and a second entry specifies a second caching policy for a second operand. The computation engine computes and stores operands in the memory hierarchy in accordance with the cache policies indicated within the operand data structure.

摘要翻译： 处理器具有包括高速缓冲存储器的相关联的存储器层级。 所述处理器包括：指令排序单元，其提取用于处理的指令;操作数数据结构，包括与由所述处理器执行的操作操作数对应的多个条目;以及计算引擎。 操作数数据结构中的多个条目中的第一条目指定第一操作数的第一高速缓存策略，第二条目指定用于第二操作数的第二高速缓存策略。 计算引擎根据操作数数据结构中指示的缓存策略计算并存储存储器层次结构中的操作数。

公开(公告)号：US07725682B2

公开(公告)日：2010-05-25

申请号：US11329320

申请日：2006-01-10

申请人： Michael Gschwind ,  Balaram Sinharoy

发明人： Michael Gschwind ,  Balaram Sinharoy

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G06F9/30181 ,  G06F9/30101 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3897 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： Methods and apparatus are provided for sharing storage and execution resources between architectural units in a microprocessor using a polymorphic function unit. A method for executing instructions in a processor having a polymorphic execution unit includes the steps of reloading a state associated with a first instruction class and reconfiguring the polymorphic execution unit to operate in accordance with the first instruction class, when an instruction of the first instruction class is encountered and the polymorphic execution unit is configured to operate in accordance with a second instruction class. The method also includes the steps of reloading a state associated with a second instruction class and reconfiguring the polymorphic execution unit to operate in accordance with the second instruction class, when an instruction of the second instruction class is encountered and the polymorphic execution unit is configured to operate in accordance with the first instruction class.

摘要翻译： 提供了用于使用多态功能单元在微处理器中的架构单元之间共享存储和执行资源的方法和装置。 一种用于在具有多态执行单元的处理器中执行指令的方法，包括以下步骤：当所述第一指令类的指令时，重新加载与第一指令类相关联的状态并重新配置所述多态执行单元以根据所述第一指令类进行操作 并且多态执行单元被配置为根据第二指令类进行操作。 该方法还包括以下步骤：当遇到第二指令类的指令时，重新加载与第二指令类相关联的状态并重新配置多项式执行单元以根据第二指令类进行操作，并且将多态执行单元配置为 按照第一个指导班进行操作。

公开(公告)号：US20100070711A1

公开(公告)日：2010-03-18

申请号：US12212935

申请日：2008-09-18

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Balaram Sinharoy

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Balaram Sinharoy

IPC分类号： G06F12/08 ,  G06F13/28

CPC分类号： G06F12/0862 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0653 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0835 ,  G06F2212/6028

摘要： A technique for performing cache injection includes monitoring addresses on a bus in response to a cache injection instruction. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block associated with the cache injection instruction.

摘要翻译： 用于执行高速缓存注入的技术包括响应于高速缓存注入指令监视总线上的地址。 当总线上的地址（与输入/输出数据相关联）对应于与高速缓存注入指令相关联的数据块的地址时，通过高速缓存获取总线上的输入/输出数据的所有权。

公开(公告)号：US07631308B2

公开(公告)日：2009-12-08

申请号：US11055850

申请日：2005-02-11

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/46

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method is disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread.

摘要翻译： 在数据处理系统中公开了一种用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性的方法。 在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。 如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。

公开(公告)号：US20090198955A1

公开(公告)日：2009-08-06

申请号：US12024486

申请日：2008-02-01

申请人： Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Balaram Sinharoy ,  Hanhong Xue

发明人： Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Balaram Sinharoy ,  Hanhong Xue

IPC分类号： G06F15/167 ,  G06F12/00

CPC分类号： G06F12/1027 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862

摘要： A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node having a second memory. The processor includes processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address, and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address. The data is transmitted via the connection mechanism connecting the two nodes independent of the processor.

摘要翻译： 分布式数据处理系统包括：（1）具有处理器的第一节点，第一存储器和异步存储器移动器逻辑; 以及连接机构，其连接（2）具有第二存储器的第二节点。 处理器包括用于完成跨节点异步存储器移动（AMM）操作的处理逻辑，其中处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并且异步存储器移动器逻辑完成 从具有第一实际地址的第一存储器中的第一存储器位置的数据的物理移动到具有第二实际地址的第二存储器中的第二存储器位置。 数据通过连接独立于处理器的两个节点的连接机制进行传输。

公开(公告)号：US20090198934A1

公开(公告)日：2009-08-06

申请号：US12024613

申请日：2008-02-01

申请人： Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Balaram Sinharoy ,  Hanhong Xue

发明人： Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Balaram Sinharoy ,  Hanhong Xue

IPC分类号： G06F12/02 ,  G06F12/14 ,  G06F9/46

CPC分类号： G06F9/30032 ,  G06F12/0831 ,  G06F12/0862 ,  G06F12/10

摘要： A data processing system has a processor and a memory coupled to the processor and an asynchronous memory mover coupled to the processor. The asynchronous memory mover has registers for receiving a set of parameters from the processor, which parameters are associated with an asynchronous memory move (AMM) operation initiated by the processor in virtual address space, utilizing a source effective address and a destination effective address. The asynchronous memory mover performs the AMM operation to move the data from a first physical memory location having a source real address corresponding to the source effective address to a second physical memory location having a destination real address corresponding to the destination effective address. The asynchronous memory mover has an associated off-chip translation mechanism. The AMM operation thus occurs independent of the processor, and the processor continues processing other operations independent of the AMM operation.

摘要翻译： 数据处理系统具有耦合到处理器的处理器和存储器以及耦合到处理器的异步存储器移动器。 异步存储器移动器具有用于从处理器接收一组参数的寄存器，这些参数与虚拟地址空间中由处理器发起的异步存储器移动（AMM）操作相关联，利用源有效地址和目的地有效地址。 异步存储器移动器执行AMM操作以将来自具有与源有效地址相对应的源实际地址的第一物理存储器位置的数据移动到具有与目的地有效地址相对应的目的地实际地址的第二物理存储器位置。 异步存储器移动器具有相关的片外转换机制。 因此，AMM操作独立于处理器，并且处理器继续处理独立于AMM操作的其他操作。