公开(公告)号：US20220238631A1

公开(公告)日：2022-07-28

申请号：US17155445

申请日：2021-01-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michael J. Zierak ,  Siva P. Adusumilli ,  Yves T. Ngu ,  Steven M. Shank

IPC: H01L49/02 ,  H01L21/762

Abstract: A structure provides a polysilicon resistor under a shallow trench isolation (STI). The structure includes the STI, a resistor in the form of a doped buried polysilicon layer under the STI, and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The structure also includes a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer. A related method is also disclosed.

公开(公告)号：US11380759B2

公开(公告)日：2022-07-05

申请号：US16939213

申请日：2020-07-27

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma Rana ,  Anthony K. Stamper ,  Johnatan A. Kantarovsky ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/763 ,  H01L21/8234 ,  H01L29/10

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

公开(公告)号：US11333558B2

公开(公告)日：2022-05-17

申请号：US16181972

申请日：2018-11-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  John J. Pekarik ,  Steven M. Shank

IPC: G01K1/02 ,  H01L45/00 ,  G01K7/22 ,  H01L27/24 ,  H01L23/522 ,  G01K7/16 ,  H01L27/00 ,  H01L23/482 ,  H01L27/06

Abstract: One device disclosed herein includes, among other things, a substrate, a first resistor comprising a first phase transition material formed above the substrate, the first phase transition material exhibiting a first dielectric phase for temperatures less than a first phase transition temperature and a first semiconductor phase for temperatures greater than the first phase transition temperature, and logic to detect a transition of the first resistor to the first semiconductor phase.

公开(公告)号：US11316045B2

公开(公告)日：2022-04-26

申请号：US16691691

申请日：2019-11-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. Stamper ,  Aaron L. Vallett ,  Steven M. Shank ,  John J. Ellis-Monaghan

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (FETS) and methods of manufacture. The structure includes: a substrate material; at least one vertically oriented gate structure extending into the substrate material and composed of a gate dielectric material and conductive gate material; and vertically oriented source/drain regions extending into the substrate material and composed of conductive dopant material and a silicide on the source/drain regions.

公开(公告)号：US20220062896A1

公开(公告)日：2022-03-03

申请号：US17006050

申请日：2020-08-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Vibhor Jain ,  Anthony Stamper ,  John Pekarik ,  John Ellis-Monaghan ,  Ramsey Hazbun

IPC: B01L3/00 ,  G01N21/05 ,  G01N21/85

Abstract: One illustrative device disclosed herein includes a semiconductor substrate, a channel that is at least partially defined by at least a portion of the semiconductor substrate, an input fluid reservoir and an output fluid reservoir, wherein the channel is in fluid communication with the input fluid reservoir and the output fluid reservoir. In this example, the device further includes a first radiation source operatively coupled to the substrate, wherein the first radiation source is adapted to generate radiation in a direction toward the channel, and at least one photodiode positioned adjacent the channel.

公开(公告)号：US11264457B1

公开(公告)日：2022-03-01

申请号：US16953897

申请日：2020-11-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark Levy ,  Siva P. Adusumilli ,  Steven M. Shank ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L21/763 ,  H01L27/06 ,  H01L21/762

Abstract: Semiconductor structures with electrical isolation and methods of forming a semiconductor structure with electrical isolation. A shallow trench isolation region, which contains a dielectric material, is positioned in a semiconductor substrate. A trench extendes through the shallow trench isolation region and to a trench bottom in the semiconductor substrate beneath the shallow trench isolation region. A dielectric layer at least partially fills the trench. A polycrystalline region, which is arranged in the semiconductor substrate, includes a portion that is positioned beneath the trench bottom.

公开(公告)号：US20210336005A1

公开(公告)日：2021-10-28

申请号：US16855236

申请日：2020-04-22

Applicant: GLOBALFOUNDRIES U.S. Inc

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L29/08 ,  H01L29/78

Abstract: The disclosure provides a field effect transistor (FET) stack with methods to form the same. The FET stack includes a first transistor over a substrate. The first transistor includes a first active semiconductor material including a first channel region between a first set of source/drain terminals, and a first gate structure over the first channel region. The first gate structure includes a first gate insulator of a first thickness above the first channel region. A second transistor is over the substrate and horizontally separated from the first transistor. A second gate structure of the second transistor may include a second gate insulator of a second thickness above a second channel region, the second thickness being greater than the first thickness. A shared gate node may be coupled to each of the first gate structure and the second gate structure.

公开(公告)号：US11158722B2

公开(公告)日：2021-10-26

申请号：US16730371

申请日：2019-12-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Steven M. Shank ,  John J. Pekarik ,  Anthony K. Stamper

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/15 ,  H01L29/16 ,  H01L29/267 ,  H01L29/10

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with an oxygen lattice structure and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the substrate; at least one oxygen film separating the sub-collector region and the collector region; an emitter region adjacent to the collector region; and a base region adjacent to the emitter region.

公开(公告)号：US20210263348A1

公开(公告)日：2021-08-26

申请号：US16799100

申请日：2020-02-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02F1/01

Abstract: Structures for a polarization switch and methods of fabricating a structure for a polarization switch. A waveguide core is located on a substrate. The waveguide core is composed of silicon nitride. An active layer is positioned proximate to a section of the waveguide core. The active layer composed of a phase change material having a first state with a first refractive index and a second state with a second refractive index.

公开(公告)号：US11049932B2

公开(公告)日：2021-06-29

申请号：US16226640

申请日：2018-12-20

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Steven M. Shank ,  Mark David Levy ,  Bruce W. Porth

IPC: H01L29/06 ,  H01L29/732 ,  H01L21/762 ,  H01L21/763 ,  H01L21/765

Abstract: The present disclosure relates to isolation structures for semiconductor devices and, more particularly, to dual trench isolation structures having a deep trench and a shallow trench for electrically isolating integrated circuit (IC) components formed on a semiconductor substrate. The semiconductor isolation structure of the present disclosure includes a semiconductor substrate, a shallow trench isolation (STI) disposed over the semiconductor substrate, a deep trench isolation (DTI) with sidewalls extending from a bottom surface of the STI and terminating in the semiconductor substrate, a multilayer dielectric lining disposed on the sidewalls of the DTI, the multilayer dielectric lining including an etch stop layer positioned between inner and outer dielectric liners, and a filler material disposed within the DTI.