公开(公告)号：US4879685A

公开(公告)日：1989-11-07

申请号：US311367

申请日：1989-02-16

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G11C7/00 ,  G11C8/04 ,  G11C11/401 ,  H01L27/10

CPC分类号： G11C7/00 ,  G11C8/04

摘要： A semiconductor memory device includes, a plurality of word lines, a plurality of bit lines and a plurality of memory cells each connected between the word lines and the bit lines at each intersection of the word lines and bit lines. A plurality of sense amplifiers, each connected to each pair of bit lines, are for amplifying a difference in potential between each of the bit lines; a plurality of bit line reset circuits, each connected to each pair of the bit lines, the difference in potential being held during the read/write cycles. A transfer mode setting circuit is for optionally selecting a first word line and thereafter selecting a second word line, and for simultaneously reading out data in each memory cell connected to the first word line onto each bit line and thereafter simultaneously writing data on each bit line amplified by the sense amplifier into each corresponding memory cell connected to the second word line.

摘要翻译： 半导体存储器件包括多个字线，多个位线和多个存储单元，每个位线和字线连接在字线和位线之间的字线和位线的每个交叉处。 每个连接到每对位线的多个读出放大器用于放大每个位线之间的电位差; 多个位线复位电路，每个连接到每对位线，在读/写周期期间电位差被保持。 传输模式设置电路用于可选地选择第一字线，然后选择第二字线，并且用于同时将连接到第一字线的每个存储单元中的数据读出到每个位线上，然后同时在每个位线上写入数据 由读出放大器放大成连接到第二字线的每个对应的存储单元。

公开(公告)号：US4807193A

公开(公告)日：1989-02-21

申请号：US81559

申请日：1987-02-25

申请人： Yoshihiro Takemae ,  Takeo Takematsu ,  Kimiaki Sato ,  Takashi Horii ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada

发明人： Yoshihiro Takemae ,  Takeo Takematsu ,  Kimiaki Sato ,  Takashi Horii ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada

IPC分类号： G11C11/409 ,  G11C7/22 ,  G11C8/18 ,  G11C11/407 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C8/18 ,  G11C7/22

摘要： A one-transistor one-capacitor type semiconductor memory device having a detection circuit for detecting the electric potential of a word line, to determine an appropriate timing for driving a sense amplifier, thereby improving the speed of memory operations.

摘要翻译： 具有用于检测字线的电位的检测电路的单晶体管单电容型半导体存储器件，以确定用于驱动读出放大器的适当定时，从而提高存储器操作的速度。

公开(公告)号：US4760281A

公开(公告)日：1988-07-26

申请号：US11947

申请日：1987-02-06

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： H03K5/02 ,  H03K5/135 ,  H03K17/04 ,  H03K19/017 ,  H03K19/096 ,  H03K19/01

CPC分类号： H03K19/01735

摘要： In a clock signal generating circuit for a semiconductor large scale integrated circuit, the clock signal generating circuit includes: a P-channel transistor and a first N-channel transistor, each connected in series between a positive side power source line and a ground side power source line; a second N-channel transistor connected between a common connection point of the P-channel transistor and the first N-channel transistor and a gate of the first N-channel transistor through a node, and a clock signal is applied to a gate of the second N-channel transistor. A capacitor is connected between the gate of the first N-channel transistor and a gate of the P-channel transistor; and a bootstrap capacitor is connected to the common connection point.

摘要翻译： 在半导体大规模集成电路的时钟信号发生电路中，时钟信号发生电路包括：P沟道晶体管和第一N沟道晶体管，其串联连接在正侧电源线和接地侧电源 源线; 连接在P沟道晶体管的公共连接点和第一N沟道晶体管之间的第二N沟道晶体管和通过节点的第一N沟道晶体管的栅极，并且时钟信号被施加到 第二N沟道晶体管。 电容器连接在第一N沟道晶体管的栅极和P沟道晶体管的栅极之间; 并且自举电容器连接到公共连接点。

公开(公告)号：US4679214A

公开(公告)日：1987-07-07

申请号：US648506

申请日：1984-09-10

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G11C19/00 ,  G11C19/08 ,  G11C19/18 ,  G11C19/28

CPC分类号： G11C19/00 ,  G11C19/184 ,  G11C19/28

摘要： A shift register having a simple circuit structure and used, for example, in a dynamic RAM device for a refresh operation. The shift register includes a plurality of circuit stages mutually connected in cascade. Each of the circuit stages includes a first transistor, for a transfer gate, which is turned on and off by a first clock signal and to which is input the output signal of the previous circuit stage. A second transistor is provided whose gate electrode is connected to the output of the first transistor, whose drain or source electrode receives a second clock signal having a different phase from the first clock signal, and whose source or drain electrode outputs an output signal. Each circuit stage also includes a reset circuit for rendering the input portion of the first transistor to a reset condition on the basis of the output signal, thereby sequentially transmitting data through each circuit stage.

摘要翻译： 一种移位寄存器，具有简单的电路结构，并且例如用于用于刷新操作的动态RAM装置中。 移位寄存器包括级联相互连接的多个电路级。 每个电路级包括用于传输门的第一晶体管，其通过第一时钟信号导通和截止，并且输入到先前电路级的输出信号。 提供了第二晶体管，其栅电极连接到第一晶体管的输出，其漏极或源极接收与第一时钟信号具有不同相位的第二时钟信号，并且其源极或漏极输出输出信号。 每个电路级还包括一个复位电路，用于根据输出信号将第一晶体管的输入部分渲染到复位状态，由此顺序地通过每个电路级发送数据。

公开(公告)号：US4572977A

公开(公告)日：1986-02-25

申请号：US560953

申请日：1983-12-13

申请人： Yoshihiro Takemae ,  Yasuo Suzuki

发明人： Yoshihiro Takemae ,  Yasuo Suzuki

IPC分类号： H03K3/0233 ,  H03K3/356 ,  H03K5/08 ,  H03K5/24 ,  G01R19/165 ,  G11C7/06

CPC分类号： H03K3/356017 ,  H03K3/35606

摘要： A comparator includes a first terminal, a second terminal, a first flip-flop circuit which inverts when the voltage applied to the first terminal becomes larger by .DELTA.V.sub.1 than the voltage applied to the second terminal, a third terminal, a fourth terminal, and a second flip-flop circuit which inverts when the voltage applied to the third terminal becomes smaller by .DELTA.V.sub.2 than the voltage applied to the fourth terminal. The comparator further includes a first switching circuit and a second switching circuit which, respectively, connect the first terminal and the fourth terminal to a voltage source to be compared, a third switching circuit and a fourth switching circuit which connect the second terminal and the third terminal to a reference voltage source. Also included is a fifth switching circuit which is commonly connected to the first flip-flop circuit and the second flip-flop circuit.

摘要翻译： 比较器包括第一端子，第二端子，当施加到第一端子的电压比施加到第二端子的电压DELTA V1变大时的第一触发器电路，第三端子，第四端子和 第二触发器电路，当施加到第三端子的电压变得比施加到第四端子的电压减小DELTA V2时反相。 比较器还包括分别将第一端子和第四端子连接到要比较的电压源的第一开关电路和第二开关电路，连接第二端子和第三端子的第三开关电路和第四开关电路 端子到参考电压源。 还包括第五开关电路，其共同连接到第一触发器电路和第二触发器电路。

公开(公告)号：US4546457A

公开(公告)日：1985-10-08

申请号：US439591

申请日：1982-11-05

申请人： Shigeki Nozaki ,  Yoshihiro Takemae

发明人： Shigeki Nozaki ,  Yoshihiro Takemae

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/40

CPC分类号： G11C11/4087 ,  G11C7/06

摘要： A metal-insulator semiconductor dynamic memory device comprising sense amplifiers arrayed on a semiconductor substrate and column decoders. Each of the column decode being provided for a plurality of sense amplifiers and selecting one or more sense amplifiers from the plurality of sense amplifiers, the column decoders being dispersed on both sides of the arrayed sense amplifiers. A plurality of control signal lines which, in order to select the sense amplifiers, control gate elements connected between bit lines connected to the sense amplifiers and data bus lines and which are disposed on both sides of the arrayed sense amplifiers. Conducting lines are also disposed between the sense amplifiers and deliver signals from the control signal lines, for selecting sense amplifiers to the gate elements on the opposite side of the control signal lines with regard to the arrayed sense amplifiers.

摘要翻译： 包括排列在半导体衬底和列解码器上的读出放大器的金属 - 绝缘体半导体动态存储器件。 每个列解码被提供给多个读出放大器并且从多个读出放大器中选择一个或多个感测放大器，列解码器分散在排列的读出放大器的两侧。 多个控制信号线，为了选择读出放大器，控制栅极元件连接在连接到读出放大器的位线和数据总线之间，并且布置在阵列读出放大器的两侧。 传导线还设置在感测放大器之间并且传送来自控制信号线的信号，用于选择感测放大器到控制信号线相对于阵列读出放大器的相反侧的门元件。

公开(公告)号：US4504929A

公开(公告)日：1985-03-12

申请号：US444499

申请日：1982-11-24

申请人： Yoshihiro Takemae ,  Tsuyoshi Ohira ,  Seiji Enomoto

发明人： Yoshihiro Takemae ,  Tsuyoshi Ohira ,  Seiji Enomoto

IPC分类号： G11C11/401 ,  G11C11/4091 ,  G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  G11C11/40

CPC分类号： G11C29/026 ,  G11C11/4091 ,  G11C29/02 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004

摘要： A dynamic semiconductor memory device provides a selected real cell, which is connected to a first of a pair of bit lines connected to a sense amplifier, and a dummy cell which is connected to a second of the pair of bit lines so as to perform a read-out operation. The dynamic semiconductor memory cell further provides an active restore circuit for pulling up the bit line potential of the bit line on the higher potential side of the pair of bit lines, in which the potential difference is increased by the read-out operation. The dynamic semiconductor cell can also provide a write-in circuit for charging the selected real cell through the bit line. A test power source pad is provided in the active restore circuit or the write in circuit so that when the reference level of the real cell is tested an optional power source can be applied from the test power source pad instead of from a normal power source.

摘要翻译： 动态半导体存储器件提供选择的实数单元，其连接到连接到读出放大器的一对位线中的第一个，以及连接到所述一对位线中的第二位的虚拟单元，以执行 读出操作。 动态半导体存储单元进一步提供有源恢复电路，用于提升位线对的位线电位，该位线位于通过读出操作增加电位差的位线对的较高电位侧。 动态半导体单元还可以提供用于通过位线对所选择的真实单元进行充电的写入电路。 在有源恢复电路或写入电路中提供测试电源焊盘，使得当测试真实单元的参考电平时，可以从测试电源焊盘而不是普通电源施加可选的电源。

公开(公告)号：US4447745A

公开(公告)日：1984-05-08

申请号：US322719

申请日：1981-11-18

申请人： Yoshihiro Takemae ,  Seiji Enomoto ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima

发明人： Yoshihiro Takemae ,  Seiji Enomoto ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima

IPC分类号： G11C11/417 ,  G06F1/04 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/418 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/096 ,  H03K5/135

CPC分类号： G11C11/4076 ,  G11C11/418 ,  H03K19/01735 ,  H03K19/01855

摘要： A semiconductor circuit used as a buffer circuit having an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during the standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit, for generating an output clock signal; the semiconductor circuit further comprising a current leak circuit for maintaining, during the standby period, the voltage of a point in the semiconductor circuit which is charged during the standby period at the value corresponding to the voltage of the power source, whereby the delay of the output clock signal, caused of the fluctuation by the voltage of the power supply during the standby period, is improved and then the high speed access time in the dynamic memory is carried out.

摘要翻译： 一种用作缓冲电路的半导体电路，具有用于接收输入时钟信号和反相输入时钟信号的输入级电路，自举电路包括用于接收输入级电路的输出并保持晶体管的栅极电压的晶体管 在待机期间处于高电平;以及输出电路，包括由所述自举电路的输出接通和断开的晶体管，用于产生输出时钟信号; 所述半导体电路还包括电流泄漏电路，用于在所述待机期间保持所述半导体电路中在所述待机期间中以与所述电源的电压对应的值被充电的点的电压，由此所述延迟 在待机期间由电源的电压引起的输出时钟信号被提高，然后执行动态存储器中的高速访问时间。

公开(公告)号：US08683165B2

公开(公告)日：2014-03-25

申请号：US12631240

申请日：2009-12-04

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C8/00 ,  G11C8/18

CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1694 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072

摘要： A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

摘要翻译： 存储器控制器根据要操作的存储器芯片的操作规范，将从控制器输出的控制器输出信号转换为存储器输入信号，并通过公共总线将结果输出到存储器芯片。 存储器控制器还通过公共总线接收从存储器芯片输出的存储器输出信号，并将接收的信号转换成可接收到控制器的控制器输入信号。 这允许单个存储器控制器访问多种类型的存储器芯片。 结果，存储器控制器可以减小芯片尺寸，降低存储器系统的成本。

公开(公告)号：US08541815B2

公开(公告)日：2013-09-24

申请号：US13351869

申请日：2012-01-17

申请人： Yoshihiro Takemae ,  Tsutomu Hosoda ,  Toshiya Sato

发明人： Yoshihiro Takemae ,  Tsutomu Hosoda ,  Toshiya Sato

IPC分类号： H01L29/66

CPC分类号： H01L29/778 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor circuit includes a first high electron mobility transistor and a second high electron mobility transistor having a negative threshold voltage, wherein a source of the second high electron mobility transistor is coupled to a gate of the first high electron mobility transistor, and a gate of the second high electron mobility transistor is coupled to a source of the first high electron mobility transistor.

摘要翻译： 晶体管电路包括具有负阈值电压的第一高电子迁移率晶体管和第二高电子迁移率晶体管，其中第二高电子迁移率晶体管的源极耦合到第一高电子迁移率晶体管的栅极，以及栅极 第二高电子迁移率晶体管耦合到第一高电子迁移率晶体管的源极。