公开(公告)号：US4807193A

公开(公告)日：1989-02-21

申请号：US81559

申请日：1987-02-25

申请人： Yoshihiro Takemae ,  Takeo Takematsu ,  Kimiaki Sato ,  Takashi Horii ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada

发明人： Yoshihiro Takemae ,  Takeo Takematsu ,  Kimiaki Sato ,  Takashi Horii ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada

IPC分类号： G11C11/409 ,  G11C7/22 ,  G11C8/18 ,  G11C11/407 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C8/18 ,  G11C7/22

摘要： A one-transistor one-capacitor type semiconductor memory device having a detection circuit for detecting the electric potential of a word line, to determine an appropriate timing for driving a sense amplifier, thereby improving the speed of memory operations.

摘要翻译： 具有用于检测字线的电位的检测电路的单晶体管单电容型半导体存储器件，以确定用于驱动读出放大器的适当定时，从而提高存储器操作的速度。

公开(公告)号：US4771407A

公开(公告)日：1988-09-13

申请号：US79061

申请日：1987-07-29

申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Hatsuo Miyahara ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada ,  Satoshi Momozono

发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Hatsuo Miyahara ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada ,  Satoshi Momozono

IPC分类号： H03K3/353 ,  G01R31/28 ,  G11C11/401 ,  G11C29/46 ,  G11C11/40

CPC分类号： G11C29/46

摘要： In a semiconductor integrated circuit having first and second power supply lines for receiving a power supply voltage, an external input terminal for receiving an input signal, and a high voltage detection circuit for detecting at the external input terminal a high voltage higher than a predetermined voltage which is higher than the power supply voltage, the high voltage detection circuit comprises an input circuit connected to the external input terminal for generating circuit for generating a reference voltage; and a differential voltage amplifier connected to receive the detection voltage and the reference voltage for amplifying the difference between the detection voltage and the reference voltage, to thereby determine whether the high voltage is applied, the input circuit comprising; a level shift element connected to the external input terminal for providing the detection voltage; an impedance element connected between the level shift element and the second power supply line; and a leak current compensating element connected between the first power supply line and the level shift element for allowing a current to flow from the first power supply line through the leak current compensating element and the impedance element to the second power supply line when the high voltage is not applied to the external input terminal.

摘要翻译： 在具有用于接收电源电压的第一和第二电源线，用于接收输入信号的外部输入端子和用于在外部输入端子处检测高于预定电压的高电压的高电压检测电路的半导体集成电路中， 高电压检测电路包括连接到外部输入端的输入电路，用于产生用于产生参考电压的电路; 连接的差分电压放大器，用于接收检测电压和参考电压，用于放大检测电压和参考电压之间的差值，从而确定是否施加高电压，输入电路包括： 连接到所述外部输入端子以提供所述检测电压的电平移动元件; 连接在电平移位元件和第二电源线之间的阻抗元件; 以及泄漏电流补偿元件，其连接在所述第一电源线和所述电平移动元件之间，用于当高电压时允许电流从所述第一电源线流过所述漏电流补偿元件和所述阻抗元件流到所述第二电源线 不适用于外部输入端子。

公开(公告)号：US4740926A

公开(公告)日：1988-04-26

申请号：US843356

申请日：1986-03-24

申请人： Yoshihiro Takemae ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

发明人： Yoshihiro Takemae ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

IPC分类号： G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C11/4094 ,  G11C11/4091

摘要： A semiconductor memory device comprises a memory cell array, a bit line charge-up circuit coupled to one of a plurality of pairs of bit lines from the memory cell array for initially charging up the one pair of bit lines to a first voltage which is lower than a power source voltage used to drive the semiconductor memory device, an active restore circuit coupled to the one pair of bit lines and a switching circuit coupled to the one pair of bit lines for disconnecting the one pair of bit lines into a first pair of bit line sections on the side of the memory cell array and a second pair of bit line sections on the side of the active restore circuit after the one pair of bit lines are initially charged up to the first voltage. The active restore circuit charges up one of the pair of bit line sections on the side of the active restore circuit to a second voltage which is higher than the first voltage depending on a datum read out from the memory cell array.

摘要翻译： 半导体存储器件包括存储单元阵列，位线充电电路，其耦合到存储单元阵列的多对位线中的一对，用于将一对位线初始充电至较低的第一电压 比用于驱动半导体存储器件的电源电压，耦合到一对位线的有效恢复电路和耦合到该一对位线的开关电路，用于将一对位线断开为第一对位 在存储单元阵列一侧的位线部分和在一对位线开始被充电至第一电压之后的有效恢复电路侧的第二对位线部分。 有源恢复电路根据从存储单元阵列读出的数据，将有源恢复电路一侧的一对位线部分中的一个充电到高于第一电压的第二电压。

公开(公告)号：US4787067A

公开(公告)日：1988-11-22

申请号：US883804

申请日：1986-07-09

申请人： Yoshihiro Takemae ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

发明人： Yoshihiro Takemae ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/408 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C11/4076

摘要： A semiconductor dynamic memory device having an improved refreshing time is disclosed wherein the memory device provides two buffer memories exclusively for the external and refresh addresses, each of the buffer memories comprising a preamplifier and a driver stage. When the falling edge of a RAS signal is detected, all the circuits are enabled in parallel, but the operation of the driver is suppressed. As soon as a CAS before RAS detector discriminates which of the falling edges of the CAS and RAS signals becomes low earlier, it sends an address driving signal to one of the drivers, and the external address or refresh address are sent immediately. Using this technique, the prior art sequential operation of discriminating the falling edges of RAS and CAS signal, sending the refresh signal, receiving it and switching the circuit from external address to refresh address is eliminated, and is replaced by a parallel operation. Thus the set up time of the dynamic memory is reduced to 1-2 n.sec. by the present invention.

摘要翻译： 公开了一种具有改善的刷新时间的半导体动态存储器件，其中存储器件专门为外部和刷新地址提供两个缓冲存储器，每个缓冲存储器包括前置放大器和驱动器级。 当检测到＆upbar＆R信号的下降沿时，所有电路并联使能，但驱动器的操作被抑制。 只要一个＆upbar＆C＆amp;上＆gt;＆R检测器识别＆upbar＆C和＆lt; upbar＆R信号的哪个下降沿较早地变低，它向其中一个驱动器发送地址驱动信号，并立即发送外部地址或刷新地址 。 使用这种技术，消除了识别＆upbar＆R和＆amp; upbar＆C信号的下降沿，发送刷新信号，接收它并将电路从外部地址切换到刷新地址的现有技术的顺序操作，并且被并行操作替代。 因此，动态存储器的建立时间减少到1-2ns。 通过本发明。

公开(公告)号：US4704706A

公开(公告)日：1987-11-03

申请号：US850330

申请日：1986-04-11

申请人： Masao Nakano ,  Yoshihiro Takemae ,  Kimiaki Sato ,  Nobumi Kodama

发明人： Masao Nakano ,  Yoshihiro Takemae ,  Kimiaki Sato ,  Nobumi Kodama

IPC分类号： H03K19/096 ,  G11C5/14 ,  G11C8/08 ,  H03K17/06 ,  G11C7/00

CPC分类号： G11C8/08

摘要： A booster circuit including a precharge capacitor (C.sub.2), a precharge driver circuit (20) having a first bootstrap circuit (C.sub.59, Q.sub.58, Q.sub.61) and precharging a voltage to the precharge capacitor in a reset mode, and an output driver circuit (19) having a switching circuit (Q.sub.21) for cutting off the output of the precharged voltage of the precharged capacitor in the reset mode and a second bootstrap circuit driving the switching circuit in an operation mode. The booster circuit further includes an additional switching circuit (Q.sub.1) for outputting a voltage to be superimposed onto the precharge voltage in the operation mode.The booster circuit may be applicable to a dynamic semiconductor memory device, for boosting a voltage of a word line at a high speed and for improving integration.

摘要翻译： 一种升压电路，包括预充电电容器（C2），具有第一自举电路（C59，Q58，Q61）的预充电驱动电路（20），并且在复位模式下向预充电电容器预充电，以及输出驱动器电路 ）具有用于在复位模式下切断预充电电容器的预充电电压的输出的开关电路（Q21）和在操作模式下驱动开关电路的第二自举电路。 升压电路还包括用于在操作模式中输出要叠加到预充电电压上的电压的附加开关电路（Q1）。 升压电路可以适用于动态半导体存储器件，用于高速提升字线的电压并改善集成度。

公开(公告)号：US4896302A

公开(公告)日：1990-01-23

申请号：US277392

申请日：1988-11-22

申请人： Kimiaki Sato ,  Yoshihiro Takemae ,  Masao Nakano ,  Nobumi Kodama

发明人： Kimiaki Sato ,  Yoshihiro Takemae ,  Masao Nakano ,  Nobumi Kodama

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/12 ,  G11C8/10 ,  G11C11/401 ,  G11C11/407

CPC分类号： G11C8/10 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/12

摘要： In a semiconductor memory device, a decoder circuit is located between first and second memory cell arrays. A sequence of driver circuits in the decoder circuit is provided as driver circuits common to the first and second memory cell arrays. The output terminal of the driver circuit is connected directly with a data input/output portion for the first memory cell array and connected with another data input/output portion for the second memory cell array through wirings traversing the decoder circuit.

摘要翻译： 在半导体存储器件中，解码器电路位于第一和第二存储单元阵列之间。 解码器电路中的一系列驱动电路被提供为第一和第二存储单元阵列共用的驱动电路。 驱动器电路的输出端子直接与用于第一存储单元阵列的数据输入/输出部分连接，并通过穿过解码器电路的布线与第二存储单元阵列的另一数据输入/输出部分相连。

公开(公告)号：US4742486A

公开(公告)日：1988-05-03

申请号：US861199

申请日：1986-05-08

申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

IPC分类号： G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/267 ,  G11C11/34 ,  G11C11/401 ,  G11C17/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C13/00

CPC分类号： G01R31/31701 ,  G11C29/46 ,  G06F11/267

摘要： In a semiconductor integrated circuit comprising an internal circuit, a device for receiving a chip select signal from the outside, a device for receiving an input signal from the outside, and a voltage detecting circuit for detecting whether or not the potential of the input signal is higher than a reference potential; the voltage detecting circuit comprises a first device for differentially comparing the potential of the input signal with the reference potential and generating an output potential in accordance with the results of the comparison, a second device for detecting a predetermined edge of the chip select signal so as to trigger the first device, and a third device for latching the output potential of the first device to the third device when the first device is triggered by the second device, the internal circuit being switched from a first mode to a second mode, or vice versa, in accordance with the output potential of the third device.

摘要翻译： 在包括内部电路的半导体集成电路中，用于从外部接收芯片选择信号的装置，用于从外部接收输入信号的装置以及检测输入信号的电位是否为 高于参考电位; 所述电压检测电路包括用于将所述输入信号的电位与所述参考电位进行差分比较并根据所述比较结果产生输出电位的第一装置，用于检测所述芯片选择信号的预定边沿的第二装置，以便 触发第一装置，以及第三装置，用于当第一装置被第二装置触发时将第一装置的输出电位锁定到第三装置，内部电路从第一模式切换到第二模式，或者副 反之亦然，根据第三器件的输出电位。

公开(公告)号：US4716549A

公开(公告)日：1987-12-29

申请号：US901680

申请日：1986-08-29

申请人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Shigeki Nozaki ,  Kimiaki Sato ,  Nobumi Kodama

发明人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Shigeki Nozaki ,  Kimiaki Sato ,  Nobumi Kodama

IPC分类号： G11C11/407 ,  G11C11/40 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4099 ,  G11C7/02 ,  G11C11/24

CPC分类号： G11C11/4099 ,  G11C11/4094

摘要： A semiconductor memory device capable of compensating for variation in a discriminating voltage of a memory cell comprising a memory cell and a gate circuit for coupling the memory cell to a bit line. The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit precharges a bit line pair with the resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state. The compensating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.

摘要翻译： 一种半导体存储器件，其能够补偿包括存储单元的存储单元和用于将存储单元耦合到位线的门电路的识别电压的变化。 该装置具有用于在复位状态下将位线对预充电到预定的合成预充电电压的预充电电路。 预充电电路对通过在复位状态下将补偿电压加到预充电电压而获得的所得预充电电压对位线对进行预充电。 补偿电压适于基于由于处于活动状态的栅极电路的寄生电容而由字线与存储电容器的电容耦合而引起的存储单元电压的变化来补偿存储单元识别电压的变化，以及 当假设寄生电容不存在时，预充电电压适于优化存储单元识别电压。

公开(公告)号：US07200059B2

公开(公告)日：2007-04-03

申请号：US11260486

申请日：2005-10-28

申请人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

发明人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

IPC分类号： G11C29/00

CPC分类号： G11C29/06 ,  G11C29/10 ,  G11C2029/0405 ,  G11C2029/1204 ,  G11C2029/3602

摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。

公开(公告)号：US20060291307A1

公开(公告)日：2006-12-28

申请号：US11260486

申请日：2005-10-28

申请人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

发明人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

IPC分类号： G11C29/00

CPC分类号： G11C29/06 ,  G11C29/10 ,  G11C2029/0405 ,  G11C2029/1204 ,  G11C2029/3602

摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。