公开(公告)号：US5751699A

公开(公告)日：1998-05-12

申请号：US669631

申请日：1996-06-24

申请人： William H. Radke

发明人： William H. Radke

IPC分类号： G06F3/00 ,  G06F13/14 ,  G06F13/40 ,  H03K19/0175 ,  H04J3/00

CPC分类号： G06F13/4022 ,  G06F13/14

摘要： A hierarchial bus structure having at least three dimensions provides improved interconnect flexibility between nodes located on one or more levels of the structure. Nodes are defined on at least first and second "horizontal" (or "H") rings, the rings being coupled by at least one "vertical" (or "V") ring. Each node is identified in terms of its (H,V) coordinates in the hierarchial interconnect structure, and an M-dimensional structure will provide an M-way multiplex unit at each node. For an M=3, e.g., three-dimensional structure, each multiplex unit has three-inputs, a Localout, a Vin, and an Hin input, and couples one of these inputs to an output port in response to a Local select arbitration signal. The output signal is coupled to Hout and Vout, and to Localin. Nodes on the same horizontal level will drive their Hin signal to Vout and Hout, whereas all other nodes receive the Vin signal. The arbitration select signals may reconfigure the overall bus structure dynamically or statically, preferably according to demand of the nodes required interconnection. Providing additional vertical rings provides redundancy and can reduce latency time. Because the multi-dimensional hierarchial structure is point-to-point, low module current may be used, the width of the metallized bus traces may be reduced, and contention-type overlap damage is minimized.

摘要翻译： 具有至少三个维度的分级总线结构在位于结构的一个或多个层次上的节点之间提供改进的互连灵活性。 在至少第一和第二“水平”（或“H”）环上限定节点，所述环由至少一个“垂直”（或“V”）环耦合。 每个节点根据分层互连结构中的（H，V）坐标进行识别，M维结构将在每个节点提供一个M路复用单元。 对于M = 3，例如三维结构，每个复用单元具有三个输入，一个Localout，一个Vin和一个Hin输入，并且响应于本地选择仲裁信号将这些输入中的一个耦合到输出端口 。 输出信号耦合到Hout和Vout，并连接到Localin。 相同水平的节点将其Hin信号驱动到Vout和Hout，而所有其他节点接收Vin信号。 仲裁选择信号可以动态地或静态地重新配置整个总线结构，优选地根据节点所需互连的需求。 提供额外的垂直环提供冗余并可以减少延迟时间。 由于多维分层结构是点对点的，所以可以使用低模块电流，可以减少金属化总线迹线的宽度，并且使竞争型重叠损伤最小化。

公开(公告)号：US5555540A

公开(公告)日：1996-09-10

申请号：US390052

申请日：1995-02-17

申请人： William H. Radke

发明人： William H. Radke

IPC分类号： G06F3/00 ,  G06F13/14 ,  G06F13/40 ,  H03K19/0175 ,  H04J3/00

CPC分类号： G06F13/4022 ,  G06F13/14

摘要： A bi-directional ring bus structure is formed on an integrated circuit from a conductive bus and M X:1 multiplexer modules (where M is an integer .gtoreq.2), coupled in a point-to-point configuration. Each module is associated with an input/output port that can communicate with the bus. Each module has an output port (Dout), and arbitration ("ARB") port, and X input ports ("LOCALout", "Din1", "Din2", . . . "Din[X-1]"). The Dout output port of an M.sub.i module is coupled, via a portion of conductive bus, to [X-1] input ports on an adjacent D.sub.i+1 module. Thus, module M.sub.0 's Dout.sub.0 output port is coupled to [X-1] input ports on module M.sub.1, module M.sub.1 's Dout.sub.1 port is coupled to [X-1] input ports of module M.sub.2, and so forth. The modules are X:1 in that the output port of each module is coupled to a chosen one of that module's X INPUT ports, as determined by the state of an arbitration select signal (ARB) coupled to the module's arbitration port. The state of the arbitration select signals defines a bus signal path between the LOCAL.sub.out input port of a module coupled to the bus, and the D.sub.in input ports of other modules. Because it is point-to-point, low module current may be used, the width of the metallized bus traces may be reduced, and contention-type overlap damage is minimized.

摘要翻译： 双向环形总线结构形成在集成电路中，导电总线和M X：1多路复用器模块（其中M为整数> / = 2），以点对点配置耦合。 每个模块与可与总线通信的输入/输出端口相关联。 每个模块都有一个输出端口（Dout）和仲裁（“ARB”）端口，X个输入端口（“LOCALout”，“Din1”，“Din2”，...“Din [X-1]”）。 Mi模块的Dout输出端口通过导电总线的一部分耦合到相邻Di + 1模块上的[X-1]输入端口。 因此，模块M0的Dout0输出端口耦合到模块M1上的[X-1]输入端口，模块M1的Dout1端口耦合到模块M2的[X-1]输入端口，等等。 这些模块是X：1，因为每个模块的输出端口被耦合到该模块的X INPUT端口中选定的一个，由耦合到模块的仲裁端口的仲裁选择信号（ARB）的状态决定。 仲裁选择信号的状态定义了耦合到总线的模块的LOCALout输入端口与其他模块的Din输入端口之间的总线信号路径。 由于是点对点的，所以可以使用低模块电流，可以减少金属化总线迹线的宽度，并且使竞争型重叠损伤最小化。

公开(公告)号：US08902648B2

公开(公告)日：2014-12-02

申请号：US13190911

申请日：2011-07-26

申请人： Tommaso Vali ,  Giovanni Santin ,  Massimo Rossini ,  William H. Radke ,  Violante Moschiano

发明人： Tommaso Vali ,  Giovanni Santin ,  Massimo Rossini ,  William H. Radke ,  Violante Moschiano

IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56

CPC分类号： G11C16/3436 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3422

摘要： Methods for determining a program window and memory devices are disclosed. One such method for determining the program window measures an amount of program disturb experienced by a particular state and determines the program window responsive to the amount of program disturb.

摘要翻译： 公开了用于确定程序窗口和存储器件的方法。 用于确定程序窗口的一种这样的方法测量由特定状态经历的程序干扰量，并且响应于程序干扰量确定程序窗口。

公开(公告)号：US08687431B2

公开(公告)日：2014-04-01

申请号：US13176886

申请日：2011-07-06

申请人： Vishal Sarin ,  William H. Radke ,  Frankie F. Roohparvar

发明人： Vishal Sarin ,  William H. Radke ,  Frankie F. Roohparvar

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454

摘要： Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.

摘要翻译： 公开了对存储器和存储器进行编程的方法。 在至少一个实施例中，通过确定所选择的单元的预定阈值电压来对存储器进行编程，其中使用所选单元的至少一个相邻单元的预定阈值电压值来确定预定阈值电压。

公开(公告)号：US20140063975A1

公开(公告)日：2014-03-06

申请号：US13600563

申请日：2012-08-31

申请人： Zhenlei Shen ,  William H. Radke

发明人： Zhenlei Shen ,  William H. Radke

IPC分类号： G11C16/04

CPC分类号： G11C16/34 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3418

摘要： The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.

摘要翻译： 本公开包括用于通过内插推断与存储器单元相关联的阈值电压分布的装置和方法。 多个实施例包括确定每个编程为多个数据状态中的一个的一组存储器单元的软数据，其中软数据包括多个不同的软数据值，确定与每个不同的数据状态相关联的存储器单元的数量 软数据值，并且通过使用与所述不同软数据值中的每一个相关联的确定量的存储器单元的内插处理来推断与所述存储器单元组相关联的阈值电压分布的至少一部分。

公开(公告)号：US08661312B2

公开(公告)日：2014-02-25

申请号：US13080299

申请日：2011-04-05

申请人： William H. Radke ,  Shuba Swaminathan ,  Brady L. Keays

发明人： William H. Radke ,  Shuba Swaminathan ,  Brady L. Keays

IPC分类号： H03M13/00

CPC分类号： H03M13/096 ,  G06F11/1008

摘要： Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.

摘要翻译： 从存储器阵列中读取数据。 在存储在数据缓冲器中之前，并行地操作汉明码检测操作和里德 - 所罗门码检测操作，以确定数据字是否具有任何错误。 并行检测操作的结果被传送到控制器电路。 如果存在可以通过汉明码校正操作来校正的错误，则执行该校正字，并且对校正字执行里德 - 所罗门码检测操作。 如果汉明码不能校正错误，则对该字执行里德 - 所罗门码修正操作。

公开(公告)号：US08635510B2

公开(公告)日：2014-01-21

申请号：US12212905

申请日：2008-09-18

申请人： William H. Radke ,  Shuba Swaminathan ,  Brady L. Keays

发明人： William H. Radke ,  Shuba Swaminathan ,  Brady L. Keays

IPC分类号： G11C29/00

CPC分类号： G06F11/10 ,  G06F11/1068

摘要： Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. Reduced complexity error detection and correction hardware and/or routines detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array. The ECC code is distributed throughout the stored data in the memory segment.

摘要翻译： 描述了通过对非系统ECC代码中的存储器行或块的数据位进行编码来促进存储器系统或设备中的数据的检测和校正的方法。 减少的复杂性错误检测和校正硬件和/或例程检测和校正存储器段中的损坏的用户数据，诸如扇区，字线行或擦除块。 用户数据不以明文格式存储在存储器阵列中。 ECC代码分布在存储器段中的所有存储的数据中。

公开(公告)号：US08531877B2

公开(公告)日：2013-09-10

申请号：US13403078

申请日：2012-02-23

申请人： William H. Radke

发明人： William H. Radke

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G06F11/1008 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C2211/5641

摘要： Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2B, rounded up to an integer, and where B is equal to the fractional number of bits represented by the programmed state.

公开(公告)号：US08429391B2

公开(公告)日：2013-04-23

申请号：US12762049

申请日：2010-04-16

申请人： Neal A. Galbo ,  Victor Y. Tsai ,  William H. Radke ,  Krishnam R. Datla

发明人： Neal A. Galbo ,  Victor Y. Tsai ,  William H. Radke ,  Krishnam R. Datla

IPC分类号： G06F9/00 ,  G06F9/24 ,  G06F13/00

CPC分类号： G06F9/5077 ,  G06F3/062 ,  G06F3/0644 ,  G06F3/0679 ,  G06F9/4401 ,  G06F12/0246 ,  G06F2212/7206

摘要： The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition.

摘要翻译： 本公开包括存储器设备和系统中的引导分区以及与其相关联的方法。 一个或多个实施例包括存储器单元的阵列，其中阵列包括引导分区和多个附加分区。 顺序逻辑单元标识符与附加分区相关联，并且与顺序逻辑单元标识符不一致的逻辑单元标识符与引导分区相关联。

公开(公告)号：US08296692B2

公开(公告)日：2012-10-23

申请号：US13021933

申请日：2011-02-07

申请人： William H. Radke

发明人： William H. Radke

IPC分类号： G06F17/50

CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C16/26

摘要： A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed back to the controller circuit that then uses the fed back signal to read the data from the data/IO bus.

摘要翻译： 控制器电路通过数据/ IO总线和控制总线耦合到存储器件。 控制器电路产生读取使能信号，该信号被发送到存储器件以指示存储器件将数据驱动到数据/ IO总线上。 读使能信号反馈到控制器电路，然后使用反馈信号从数据/ IO总线读取数据。