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488 条记录 (耗时 0.03 秒)

    Self-aligned process for capping copper lines
    103.
    发明授权
    Self-aligned process for capping copper lines 失效
    自动对线加工铜线

    公开(公告)号：US5310602A

    公开(公告)日：1994-05-10

    申请号：US960627

    申请日：1992-10-13

    申请人： Jian Li ,  James W. Mayer ,  Evan G. Colgan ,  Jeffrey P. Gambino

    发明人： Jian Li ,  James W. Mayer ,  Evan G. Colgan ,  Jeffrey P. Gambino

    IPC分类号： H01L21/768 ,  H01L23/532 ,  B32B9/00

    CPC分类号： H01L21/76858 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/238 ,  Y10T428/239 ,  Y10T428/24917

    摘要： The present invention features a process and a resulting article in which copper-based multilevel interconnects are fabricated. The copper-based multilevel interconnect formed by the inventive process first includes the process step of depositing a pattern of copper lines upon or in an applicable substrate, such as silicon dioxide. The copper lines are approximately one micron thick. The lines are coated with approximately 50 to 100 nm of titanium by sputter deposition, and undergo subsequent annealing at approximately 300.degree. C. to 400.degree. C. in an argon ambient. The titanium and copper layers are annealed to provide a Cu.sub.3 Ti alloy at the copper/titanium junction. The unreacted titanium between the copper features is then stripped away by dry etching with fluorine-based etch. The remaining Cu.sub.3 Ti alloy is subsequently transformed into TiN(O) and copper by a rapid thermal annealing in an NH.sub.3 atmosphere at an approximate temperature of below 650.degree. C., and then usually at temperatures ranging from between 550.degree. C. to 650.degree. C. for approximately five minutes. The copper lines are thereby capped with a layer of TiN(O), since oxygen is incorporated into the TiN layer during the heat treatment. The TiN(O) layer is more effective as a diffusion barrier than is TiN.

    摘要翻译： 本发明的特征在于制造铜基多层互连的工艺和所得到的制品。 由本发明的方法形成的基于铜的多层互连首先包括将铜线图案沉积在诸如二氧化硅之类的适用基底上或其中的工艺步骤。 铜线约为1微米厚。 线通过溅射沉积涂覆有约50至100nm的钛，并在氩气氛围中在约300℃至400℃下进行随后的退火。 对钛和铜层进行退火以在铜/钛结处提供Cu 3 Ti合金。 然后通过用氟基蚀刻的干蚀刻剥离铜特征之间的未反应的钛。 剩余的Cu3Ti合金随后在NH3气氛中在大约650℃左右的快速热退火下转化成TiN（O）和铜，然后通常在550℃至650℃的温度范围内 约五分钟。 因此，铜线由TiN（O）层覆盖，因为在热处理期间氧被并入到TiN层中。 作为扩散阻挡层，TiN（O）层比TiN更有效。

    Process for fabricating copper interconnects in ultra large scale integrated (ULSI) circuits
    104.
    发明授权
    Process for fabricating copper interconnects in ultra large scale integrated (ULSI) circuits 失效
    在超大规模集成（ULSI）电路中制造铜互连的工艺

    公开(公告)号：US5277985A

    公开(公告)日：1994-01-11

    申请号：US790971

    申请日：1991-11-12

    申请人： Jian Li ,  Evan Colgan ,  James W. Mayer

    发明人： Jian Li ,  Evan Colgan ,  James W. Mayer

    IPC分类号： H01L21/768 ,  H01L23/532 ,  B32B9/00

    CPC分类号： H01L21/76867 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/24917

    摘要： The present invention features low-temperature, self-encapsulated, copper interconnect lines on silicon substrates of Ultra-Large Scale Integration (ULSI) circuits. The interconnect lines are a product of a process that includes the following steps: (a) alloying the copper with titanium in an approximate 10 atomic weight percentage of titanium; (b) depositing a layer of the copper/titanium alloy upon a silicon dioxide/silicon substrate of a ULSI circuit; (c) patterning the copper/titanium layer to form interconnect lines on the substrate; (d) forming a titanium rich surface film on the copper interconnect lines by rapid heating of the copper/titanium interconnect lines at an approximate ramping rate of between 60.degree. and 80.degree. C./minute; and (e) nitriding the titanium rich surface of the interconnect lines in an ammonia atmosphere at low temperatures in an approximate range of between 450.degree. to 650.degree. C. for about 15 to 40 minutes, to form a titanium nitride encapsulating layer about said copper interconnect lines.

    摘要翻译： 本发明在超大规模集成（ULSI）电路的硅衬底上具有低温，自封装的铜互连线。 互连线是包括以下步骤的工艺的产物：（a）将铜与约10原子量的钛的钛合金化; （b）将铜/钛合金层沉积在ULSI电路的二氧化硅/硅衬底上; （c）图案化铜/钛层以在衬底上形成互连线; （d）通过铜/钛互连线以60摄氏度到80摄氏度/分钟的近似斜率的快速加热在铜互连线上形成富钛表面膜; 并且（e）在氨气气氛中在约450至650℃的近似范围内的低温下将互连线的富钛表面渗氮约15至40分钟，以形成围绕所述铜的氮化钛封装层 互连线。

    HOLE-BLOCKING MATERIALS FOR ORGANIC LIGHT EMITTING DIODES
    107.
    发明申请
    HOLE-BLOCKING MATERIALS FOR ORGANIC LIGHT EMITTING DIODES 有权

    公开(公告)号：US20210193947A1

    公开(公告)日：2021-06-24

    申请号：US16756207

    申请日：2018-10-17

    申请人： Jian Li

    发明人： Jian Li

    IPC分类号： H01L51/50 ,  H01L51/00

    摘要： An organic light emitting device including an emissive layer including a blue phosphorescent emitter, an electron transport layer, and a hole blocking layer between the emissive layer and the electron transport layer, wherein the hole blocking layer comprises a tetradentate palladium complex.

    PHOSPHORESCENT EXCIMERS WITH PREFERRED MOLECULAR ORIENTATION AS MONOCHROMATIC EMITTERS FOR DISPLAY AND LIGHTING APPLICATIONS
    108.
    发明申请
    PHOSPHORESCENT EXCIMERS WITH PREFERRED MOLECULAR ORIENTATION AS MONOCHROMATIC EMITTERS FOR DISPLAY AND LIGHTING APPLICATIONS 有权

    公开(公告)号：US20210193936A1

    公开(公告)日：2021-06-24

    申请号：US16756219

    申请日：2018-10-17

    申请人： Jian Li

    发明人： Jian Li

    IPC分类号： H01L51/00 ,  C09K11/06 ,  C09K11/02 ,  C07F15/00

    摘要： An organic light emitting diode having a substrate, a first electrode, a hole transporting layer proximate the first electrode, a second electrode, an electron transporting layer proximate the second electrode, and an emissive layer between the hole transporting layer and the electron transporting layer. The emissive layer includes a square planar tetradentate platinum or palladium complex, and excimers formed by two or more of the complexes are aligned such that emitting dipoles of the excimers are substantially parallel to a surface of the substrate.