公开(公告)号：US08575698B2

公开(公告)日：2013-11-05

申请号：US13283308

申请日：2011-10-27

申请人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L27/12

CPC分类号： H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

摘要： A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.

摘要翻译： 场效应晶体管结构，其使用薄绝缘体上半导体通道来控制器件的静电完整性。 嵌入的应力源在源极/漏极区域中从硅衬底中的模板通过在源极/漏极区域中的掩埋氧化物中形成的开口外延生长。 此外，在嵌入式应力器和位于沟道正下方的掩埋氧化物层下面的半导体区域之间形成介电层，以抑制结电容和漏电。

公开(公告)号：US20130082328A1

公开(公告)日：2013-04-04

申请号：US13251783

申请日：2011-10-03

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78654

摘要： Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.

摘要翻译： 公开了包括应激源的晶体管器件。 一个这样的晶体管器件包括沟道区，电介质层和半导体衬底。 沟道区域被配置为在源极区域和漏极区域之间提供导电沟道。 此外，电介质层在沟道区下方，并被配置为使沟道区电绝缘。 此外，半导体衬底在沟道区域下方和介电层下方包括在半导体衬底的顶表面处的位错缺陷，其中位错缺陷共同定向以在沟道区域施加压缩应变，使得载流子 渠道区域的移动性得到增强。

公开(公告)号：US08338260B2

公开(公告)日：2012-12-25

申请号：US12760250

申请日：2010-04-14

申请人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam Shahidi

发明人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam Shahidi

IPC分类号： H01L21/336

CPC分类号： H01L29/78654 ,  H01L21/76283 ,  H01L29/66772 ,  H01L29/78618

摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.

摘要翻译： 提供一种晶体管，其包括衬底上方的掩埋氧化物层。 硅层在掩埋氧化物层之上。 栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。 氮化物衬垫与栅堆叠相邻。 氧化物衬垫与氮化物衬垫相邻。 一组具有包括硅层的一部分的部分的凸起的源/漏区。 所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

公开(公告)号：US20120286364A1

公开(公告)日：2012-11-15

申请号：US13104542

申请日：2011-05-10

申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/8238

CPC分类号： H01L27/0727 ,  H01L21/823418 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203

摘要： A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.

摘要翻译： 一种方法包括在半导体衬底中形成隔离区以限定第一场效应晶体管（FET）区域，第二FET区域和二极管区域，在第一FET区域中形成第一栅极堆叠，在第二FET区域中形成第二栅极堆叠 FET区域，在所述第二FET区域和所述第二栅极堆叠上形成间隔材料层，在所述第一FET区域中形成第一源极区域和第一漏极区域，以及使用第一外延生长工艺在所述二极管区域中形成第一二极管层 在所述第一源极区域，所述第一漏极区域，所述第一栅极堆叠层和所述第一二极管层的一部分上形成硬掩模层，以及在所述第一FET区域中形成第二源极区域和第二漏极区域，以及在所述第一FET区域中形成第二二极管层 使用第二外延生长工艺在第一二极管层上。

公开(公告)号：US20120261754A1

公开(公告)日：2012-10-18

申请号：US13086459

申请日：2011-04-14

申请人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0603 ,  H01L29/1054 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78

摘要： MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.

摘要翻译： 公开了用于制造具有凹陷沟道和突然结的MOSFET的MOSFET和方法。 该方法包括在虚拟门就位的情况下创建源极和漏极扩展。 源极/漏极延伸部分产生与硅衬底的扩散结。 该方法通过去除伪栅极并蚀刻硅衬底中的凹槽来继续。 凹部与源极和漏极结的至少一部分相交。 然后，通过生长硅膜以至少部分地填充凹部而形成通道。 该通道与源极和漏极具有尖锐的结，而沟道下方的未蚀刻的硅具有与源极和漏极的扩散结。 因此，可以产生在相同晶体管中具有两个结区的尖锐和扩散的MOSFET。

公开(公告)号：US20120235239A1

公开(公告)日：2012-09-20

申请号：US13049491

申请日：2011-03-16

申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/7839

摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.

摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化的栅极结构，在邻近栅极结构的源极侧的半导体衬底上形成凸起的源极区域，并在图案化的栅极上形成凸起的源极区域上的硅化物接触 并且在与栅极结构的漏极侧相邻的半导体衬底上。 因此，限定了具有漏极侧肖特基接触和升高的源极侧欧姆接触的混合场效应晶体管（FET）结构。

公开(公告)号：US08546203B1

公开(公告)日：2013-10-01

申请号：US13551100

申请日：2012-07-17

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Nicolas Loubet ,  Amlan Majumdar ,  Stefan Schmitz

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Nicolas Loubet ,  Amlan Majumdar ,  Stefan Schmitz

IPC分类号： H01L21/00

CPC分类号： H01L21/84 ,  H01L29/66628

摘要： Method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. Low quality nitride and high quality nitride are formed on the semiconductor structure. The high quality nitride in the NFET portion is damaged by ion implantation to facilitate its removal. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The high quality nitride in the PFET portion is damaged by ion implantation to facilitate its removal. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

摘要翻译： 形成半导体结构的方法包括具有PFET部分和NFET部分的极薄的绝缘上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，与 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。 在半导体结构上形成低质量的氮化物和高质量的氮化物。 NFET部分中的高质量氮化物被离子注入损坏以便于其去除。 在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的高质量氮化物被离子注入损坏以便于其去除。 扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

公开(公告)号：US08304301B2

公开(公告)日：2012-11-06

申请号：US12621299

申请日：2009-11-18

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66636 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer. Epitaxially growing the extremely thin semiconductor layer on the Ge layer ensures good thickness control across the wafer. This process could be used for SOI or bulk wafers.

摘要翻译： 公开了半导体器件和制造半导体器件的方法。 在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。 该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。 以这种方式，半导体层成为非常薄的绝缘体上半导体层。 在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。 在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。 在Ge层上外延生长极薄的半导体层确保跨晶片的良好的厚度控制。 该工艺可用于SOI或体晶片。

公开(公告)号：US08169024B2

公开(公告)日：2012-05-01

申请号：US12542771

申请日：2009-08-18

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Pranita Kulkarni ,  Ghavam Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Pranita Kulkarni ,  Ghavam Shahidi

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method of fabricating a semiconductor device is provided in which the channel of the device is present in an extremely thin silicon on insulator (ETSOI) layer, i.e., a silicon containing layer having a thickness of less than 10.0 nm. In one embodiment, the method may begin with providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10.0 nm. A gate structure is formed directly on the first semiconductor layer. A in-situ doped semiconductor material is formed on the first semiconductor layer adjacent to the gate structure. The dopant from the in-situ doped semiconductor material is then diffused into the first semiconductor layer to form extension regions. The method is also applicable to finFET structures.

摘要翻译： 提供一种制造半导体器件的方法，其中器件的沟道存在于极薄的绝缘体上（ETSOI）层，即厚度小于10.0nm的含硅层中。 在一个实施例中，该方法可以从提供具有覆盖介电层的至少第一半导体层的衬底开始，其中第一半导体层具有小于10.0nm的厚度。 栅极结构直接形成在第一半导体层上。 在与栅极结构相邻的第一半导体层上形成原位掺杂的半导体材料。 然后将来自原位掺杂半导体材料的掺杂剂扩散到第一半导体层中以形成延伸区域。 该方法也适用于finFET结构。

公开(公告)号：US08685804B2

公开(公告)日：2014-04-01

申请号：US13251783

申请日：2011-10-03

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78654

摘要： Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.