利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

109 条记录 (耗时 0.026 秒)

    Method of making an integrated circuit with oxidizable trench liner
    101.
    发明授权
    Method of making an integrated circuit with oxidizable trench liner 失效
    制造具有可氧化沟槽衬垫的集成电路的方法

    公开(公告)号：US5926717A

    公开(公告)日：1999-07-20

    申请号：US763313

    申请日：1996-12-10

    申请人： Mark W. Michael ,  Robert Dawson ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  William S. Brennan

    发明人： Mark W. Michael ,  Robert Dawson ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  William S. Brennan

    IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/62

    CPC分类号： H01L21/76227

    摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a trench in the semiconductor substrate between said first active region and said second active region. A first dielectric layer is then formed on said trench and a polysilicon layer is deposited on said first dielectric layer. The polysilicon layer is then thermally oxidized to form a second dielectric layer. Preferably the first dielectric is a thermal oxide 40 to 500 angstroms in thickness consuming less than 200 angstroms of said first active region and said second active region. The polysilicon layer is preferably between 1000 to 2000 angstroms.

    摘要翻译： 一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。 该方法包括在所述第一有源区和所述第二有源区之间的半导体衬底中形成沟槽。 然后在所述沟槽上形成第一电介质层，并且在所述第一电介质层上沉积多晶硅层。 然后将多晶硅层热氧化以形成第二介电层。 优选地，第一电介质是厚度为40-500埃的热氧化物，其消耗小于200埃的所述第一有源区和所述第二活性区。 多晶硅层优选为1000〜2000埃。

    Method for achieving global planarization by forming minimum mesas in large field areas
    102.
    发明授权
    Method for achieving global planarization by forming minimum mesas in large field areas 失效
    通过在大场区域形成最小台面来实现全局平坦化的方法

    公开(公告)号：US5926713A

    公开(公告)日：1999-07-20

    申请号：US923322

    申请日：1997-09-04

    申请人： Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark W. Michael ,  William S. Brennan

    发明人： Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark W. Michael ,  William S. Brennan

    IPC分类号： H01L21/3105 ,  H01L21/336 ,  H01L21/762

    CPC分类号： H01L29/66712 ,  H01L21/31053 ,  H01L21/76229

    摘要： An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of silicon risers formed in wide isolation regions. The space between silicon risers are ideally suited for optimal fill of a dielectric deposited across the semiconductor topography, i.e., across and between the silicon risers formed between active areas. The silicon risers, and optimally dimensioned trenches extending between the risers, enhance the planarity of the deposited dielectric. The deposited dielectric upper surface includes recesses of minimal elevational disparity, wherein the recesses are closely spaced in alignment directly above the trenches formed between silicon risers. The recesses can be readily removed by a chemical-mechanical polishing step with minimal deformity to the polishing pad, resulting in global planarization of the dielectric upper surface.

    摘要翻译： 提供隔离技术用于改善沟槽隔离区域相对于相邻硅台面的整体平面度。 分离过程导致在宽隔离区域中形成间隔开的多个硅提升管。 硅提升管之间的空间理想地适用于跨半导体形貌沉积的电介质的最佳填充，即在活性区域之间形成的硅提升板之间和之间。 硅立管和在立管之间延伸的最佳尺寸的沟槽增强了沉积的电介质的平面性。 沉积的电介质上表面包括具有最小高度差异的凹槽，其中凹槽在硅立管之间形成的沟槽的正上方紧密间隔开。 可以通过化学机械抛光步骤容易地去除凹部，对抛光垫具有最小的变形，导致电介质上表面的全局平坦化。

    Method of making an igfet with selectively doped multilevel polysilicon gate
    104.
    发明授权
    Method of making an igfet with selectively doped multilevel polysilicon gate 失效
    用选择性掺杂多电平多晶硅栅极制造igfet的方法

    公开(公告)号：US5885887A

    公开(公告)日：1999-03-23

    申请号：US847752

    申请日：1997-04-21

    申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

    发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/38

    CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L21/823842 ,  H01L29/42376

    摘要： A method of making an IGFET with a selectively doped multilevel polysilicon gate that includes upper and lower polysilicon gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a a lower polysilicon layer on the gate insulator, forming a first masking layer over the lower polysilicon layer, etching the lower polysilicon layer through openings in the first masking layer using the first masking layer as an etch mask for a portion of the lower polysilicon layer that forms the lower polysilicon gate level over the active region, removing the first masking layer, forming the upper polysilicon gate level on the lower polysilicon gate level after removing the first masking layer, introducing a dopant into the upper polysilicon gate level without introducing the dopant into the substrate, diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level, and forming a source and drain in the active region. Advantageously, the lower polysilicon gate level has both an accurately defined length to provide the desired channel length and a well-controlled doping concentration to provide the desired threshold voltage.

    摘要翻译： 公开了一种制造具有选择性掺杂多电平多晶硅栅极的IGFET的方法，其包括上和下多晶硅栅极电平。 该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上形成下部多晶硅层，在下部多晶硅层上形成第一掩蔽层，通过下部多晶硅层的开口蚀刻下部多晶硅层 所述第一掩模层使用所述第一掩模层作为用于在所述有源区上形成所述下多晶硅栅极电平的所述下多晶硅层的一部分的蚀刻掩模，去除所述第一掩模层，在所述下多晶硅栅极上形成所述上多晶硅栅极电平 在去除第一掩模层之后，将掺杂剂引入上多晶硅栅极级，而不将掺杂剂引入衬底中，将掺杂剂从上多晶硅栅极级扩散到下多晶硅栅极电平，并在活性层中形成源极和漏极 地区。 有利地，下多晶硅栅极电平具有精确限定的长度以提供期望的沟道长度和良好控制的掺杂浓度以提供期望的阈值电压。

    Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process
    105.
    发明授权
    Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process 失效
    通过单个通孔蚀刻和单次填充工艺形成集成电路的多层互连结构的方法

    公开(公告)号：US5851913A

    公开(公告)日：1998-12-22

    申请号：US655246

    申请日：1996-06-05

    申请人： William S. Brennan ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael

    发明人： William S. Brennan ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/768 ,  H01L21/76807

    摘要： A multilevel interconnect structure is provided. The multilevel interconnect structure includes two, three or more levels of conductors formed according to at least two exemplary embodiments. According to one embodiment, the contact structure which links conductors on one level to an underlying level is formed by a single via etch step followed by a fill step separate from a fill step used in filling the via. In this embodiment, the via is filled with a conductive material which forms a plug separate from the material used in forming the interconnect. In another exemplary embodiment, the step used in filling the via can be the same as that used in forming the interconnect. In either instance, a via is formed through a first dielectric to underlying conductors. A second dielectric is patterned upon the first dielectric and serves to laterally bound the fill material used in producing the overlying interconnect. Regardless of the process sequence chosen, the interlevel dielectric structure is left substantially planar in readiness for subsequent interconnect levels dielectically deposited thereon.

    摘要翻译： 提供了多层互连结构。 多层互连结构包括根据至少两个示例性实施例形成的两层，三层或更多级的导体。 根据一个实施例，通过单个通孔蚀刻步骤形成将一个层上的导体连接到下层的接触结构，随后是与用于填充通孔的填充步骤分离的填充步骤。 在该实施例中，通孔填充导电材料，该导电材料形成与用于形成互连件的材料分开的插头。 在另一个示例性实施例中，用于填充通孔的步骤可以与在形成互连中使用的步骤相同。 在任一情况下，通孔通过第一电介质形成到下面的导体。 在第一电介质上构图第二电介质，并且用于横向地限制用于制造上覆互连的填充材料。 不管选择的工艺顺序如何，层间电介质结构留在基本上平坦的准备中，用于介于其上的后续互连层。

    Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric
    106.
    发明授权
    Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric 失效
    具有基本上均匀的掺杂分布的半导体栅极导体对掺杂剂渗透到下面的栅极电介质中具有最小的敏感性

    公开(公告)号：US5851889A

    公开(公告)日：1998-12-22

    申请号：US792714

    申请日：1997-01-30

    申请人： Mark W. Michael ,  Robert Dawson

    发明人： Mark W. Michael ,  Robert Dawson

    IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/28035 ,  H01L21/823842

    摘要： A semiconductor fabrication process is presented which optimizes the position of impurities within a gate conductor a the source/drain straddling the gate conductor. Optimal positioned is achieved by using separate implants of different energies depending upon whether the gate conductor connotes a PMOS or NMOS transistor. A layer of polysilicon used to form the gate conductor is doped before patterning so that the source and drain regions are protected. A low energy implant is performed when implanting a fast diffuser such as boron, and a high energy implant is performed when implanting a slow diffuser like arsenic. This enables optimum positioning of the impurities throughout the gate conductor cross-section after heat cycles are applied. Fast diffusers are initially placed far from the bottom surface of the polysilicon, and diffuse near the bottom surface of the polysilicon when heat is applied. Slow diffusers are initially placed closer to the bottom surface of the polysilicon, since they do not diffuse as readily. The source and drain regions are implanted using a very low energy implant, separately from the polysilicon implants, to produce a desirable shallow source and drain region within the semiconductor substrate.

    摘要翻译： 提出了一种半导体制造工艺，其优化栅极导体内杂质的位置，栅极导体中跨越栅极导体的源极/漏极。 取决于栅极导体是指PMOS还是NMOS晶体管，通过使用不同能量的单独注入来实现最佳定位。 用于形成栅极导体的多晶硅层在图案化之前被掺杂，使得源极和漏极区域受到保护。 当植入诸如硼的快速扩散器时执行低能量注入，并且当植入像砷这样的慢扩散器时执行高能量注入。 这使得在施加热循环之后，杂质在整个栅极导体横截面中的最佳定位。 最初放置快速扩散器远离多晶硅的底表面，并在加热时在多晶硅的底表面附近扩散。 缓慢扩散器最初放置得更靠近多晶硅的底表面，因为它们不会容易地扩散。 使用与多晶硅植入物分开的非常低能量的注入来注入源极区和漏极区，以在半导体衬底内产生期望的浅源极和漏极区。

    Multilevel interconnect structure of an integrated circuit formed by a single via etch and dual fill process
    109.
    发明授权
    Multilevel interconnect structure of an integrated circuit formed by a single via etch and dual fill process 失效
    由单通道蚀刻和双重填充工艺形成的集成电路的多层互连结构

    公开(公告)号：US5679605A

    公开(公告)日：1997-10-21

    申请号：US658458

    申请日：1996-06-05

    申请人： William S. Brennan ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael

    发明人： William S. Brennan ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael

    IPC分类号： H01L21/768 ,  H01L21/441

    CPC分类号： H01L21/76877

    摘要： A multilevel interconnect structure is provided. The multilevel interconnect structure includes two, three or more levels of conductors formed according to at least two exemplary embodiments. According to one embodiment, the contact structure which links conductors on one level to an underlying level is formed by a single via etch step followed by a fill step separate from a fill step used in filling the via. In this embodiment, the via is filled with a conductive material which forms a plug separate from the material used in forming the interconnect. In another exemplary embodiment, the step used in filling the via can be the same as that used in forming the interconnect. In either instance, a via is formed through a first dielectric to underlying conductors. A second dielectric is patterned upon the first dielectric and serves to laterally bound the fill material used in producing the overlying interconnect. Regardless of the process sequence chosen, the interlevel dielectric structure is left substantially planar in readiness for subsequent interconnect levels dielectically deposited thereon.

    摘要翻译： 提供了多层互连结构。 多层互连结构包括根据至少两个示例性实施例形成的两层，三层或更多级的导体。 根据一个实施例，通过单个通孔蚀刻步骤形成将一个层上的导体连接到下层的接触结构，随后是与用于填充通孔的填充步骤分离的填充步骤。 在该实施例中，通孔填充导电材料，该导电材料形成与用于形成互连件的材料分开的插头。 在另一个示例性实施例中，用于填充通孔的步骤可以与在形成互连中使用的步骤相同。 在任一情况下，通孔通过第一电介质形成到下面的导体。 在第一电介质上构图第二电介质，并且用于横向地限制用于制造上覆互连的填充材料。 不管选择的工艺顺序如何，层间电介质结构留在基本上平坦的准备中，用于介于其上的后续互连层。