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公开(公告)号：US20240130143A1
公开(公告)日：2024-04-18
申请号：US17968744
申请日：2022-10-18
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Agostino Pirovano , Matteo Impalà , Mattia Robustelli , Fabio Pellizzer
CPC classification number: H01L27/2481 , H01L45/06 , H01L45/143 , H01L45/1683
Abstract: A single memory chip including both memory and storage capabilities on the single chip and accompanying process for forming a memory array including both capabilities is disclosed. In particular, the single chip may incorporate the use of two different chalcogenide materials deposited thereon to implement the memory and storage capabilities. Chalcogenide materials provide flexibility on cell performance, such as by changing the chalcogenide material composition. For the single memory chip, one type of chalcogenide material may be utilized to create memory cells and another type of chalcogenide material may be utilized to create storage cells. The process for forming the memory array includes forming first and second openings in a starting structure and performing a series of etching and deposition steps on the structure to form the memory and storage cells using the two different chalcogenide compositions. The memory and storage cells are independently addressable via wordline and bitline selection.
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公开(公告)号：US11769551B2
公开(公告)日：2023-09-26
申请号：US17399853
申请日：2021-08-11
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
IPC: G11C11/56 , G11C13/00 , G11C11/402 , G11C11/4074 , G11C27/00 , G11C7/00 , H01L45/00 , H10N70/20 , H10N70/00
CPC classification number: G11C11/5678 , G11C13/004 , G11C13/0004 , G11C13/0069 , H10N70/24 , H10N70/826 , H10N70/882 , G11C13/0002 , G11C13/0007 , G11C2013/0052 , G11C2013/0092 , G11C2213/30 , G11C2213/31 , G11C2213/71
Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US11763886B2
公开(公告)日：2023-09-19
申请号：US17499290
申请日：2021-10-12
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Andrea Redaelli , Agostino Pirovano , Fabio Pellizzer , Mario Allegra , Paolo Fantini
CPC classification number: G11C13/0069 , G11C11/5678 , G11C13/004 , G11C13/0004 , G11C13/0038 , G11C13/0061 , H10B63/80 , G11C13/0026 , G11C13/0028 , G11C2013/0052 , G11C2013/0092 , G11C2213/30 , G11C2213/71 , H10N70/841 , H10N70/882
Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US11587979B2
公开(公告)日：2023-02-21
申请号：US17144669
申请日：2021-01-08
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli
Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
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公开(公告)号：US11443799B2
公开(公告)日：2022-09-13
申请号：US16436734
申请日：2019-06-10
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Russell L. Meyer , Agostino Pirovano , Andrea Redaelli , Lorenzo Fratin , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
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Patent Agency Ranking
公开(公告)号：US11417841B2
公开(公告)日：2022-08-16
申请号：US16539932
申请日：2019-08-13
Applicant: Micron Technology, Inc.
Inventor： Stephen W. Russell , Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer , Lorenzo Fratin
Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.
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公开(公告)号：US20220189551A1
公开(公告)日：2022-06-16
申请号：US17685219
申请日：2022-03-02
Applicant: Micron Technology, Inc.
Inventor： Hernan A. Castro , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.
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公开(公告)号：US11302748B2
公开(公告)日：2022-04-12
申请号：US16575743
申请日：2019-09-19
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Agostino Pirovano , Andrea Redaelli
Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.
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公开(公告)号：US11120870B2
公开(公告)日：2021-09-14
申请号：US16998240
申请日：2020-08-20
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.
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公开(公告)号：US20210273015A1
公开(公告)日：2021-09-02
申请号：US17320785
申请日：2021-05-14
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Andrea Redaelli , Agostino Pirovano
Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.
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