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    MEMORY DEVICE HAVING 2-TRANSISTOR MEMORY CELL AND ACCESS LINE PLATE
    102.
    发明申请
    MEMORY DEVICE HAVING 2-TRANSISTOR MEMORY CELL AND ACCESS LINE PLATE 有权

    公开(公告)号：US20220278103A1

    公开(公告)日：2022-09-01

    申请号：US17745298

    申请日：2022-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/105 ,  H01L27/12 ,  H01L29/788 ,  H01L29/24 ,  H01L29/786

    Abstract: Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.

    Transistors including oxide semiconductive materials, and related microelectronic devices, memory devices, electronic systems, and methods
    103.
    发明授权
    Transistors including oxide semiconductive materials, and related microelectronic devices, memory devices, electronic systems, and methods 有权

    公开(公告)号：US11430895B2

    公开(公告)日：2022-08-30

    申请号：US16891462

    申请日：2020-06-03

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Guangyu Huang ,  Haitao Liu ,  Akira Goda

    IPC: H01L29/786 ,  H01L27/11529 ,  H01L27/11573 ,  H01L29/66

    Abstract: A transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.

    Microelectronic devices including passing word line structures, and related electronic systems and methods
    104.
    发明授权
    Microelectronic devices including passing word line structures, and related electronic systems and methods 有权

    公开(公告)号：US11430793B2

    公开(公告)日：2022-08-30

    申请号：US16899339

    申请日：2020-06-11

    Applicant: Micron Technology, Inc.

    Inventor： Deepak Chandra Pandey ,  Venkata Naveen Kumar Neelapala ,  Haitao Liu

    IPC: H01L27/108

    Abstract: A microelectronic device comprises a first pillar of a semiconductive material, a second pillar of the semiconductive material adjacent to the first pillar of the semiconductive material, an active word line extending between the first pillar and the second pillar, and a passing word line extending on a side of the second pillar opposite the active word line, the passing word line extending into an isolation region within the semiconductive material, the isolation region comprising a lower portion and an upper portion having a substantially circular cross-sectional shape and a larger lateral dimension than the lower portion. Related microelectronic devices, electronic systems, and methods are also described.

    MICROELECTRONIC DEVICES WITH DOPANT EXTENSIONS NEAR A GIDL REGION BELOW A TIER STACK, AND RELATED METHODS AND SYSTEMS
    105.
    发明申请
    MICROELECTRONIC DEVICES WITH DOPANT EXTENSIONS NEAR A GIDL REGION BELOW A TIER STACK, AND RELATED METHODS AND SYSTEMS 有权

    公开(公告)号：US20220238547A1

    公开(公告)日：2022-07-28

    申请号：US17158859

    申请日：2021-01-26

    Applicant: Micron Technology, Inc.

    Inventor： Albert Fayrushin ,  Haitao Liu ,  Chris M. Carlson

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

    Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material. A vertical extension of the doped material protrudes upward to an interface with the channel material at elevation within the stack structure (e.g., an elevation proximate or laterally overlapping in elevation at least one source-side GIDL region). The microelectronic device structure may be formed by a method that includes forming a lateral opening through cell materials of the pillar, recessing the channel material to form a vertical recess, and forming the doped material in the vertical recess. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

    MEMORY DEVICE HAVING SHARED ACCESS LINE FOR 2-TRANSISTOR VERTICAL MEMORY CELL
    106.
    发明申请
    MEMORY DEVICE HAVING SHARED ACCESS LINE FOR 2-TRANSISTOR VERTICAL MEMORY CELL 有权

    公开(公告)号：US20220223605A1

    公开(公告)日：2022-07-14

    申请号：US17712674

    申请日：2022-04-04

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

    IPC: H01L27/108

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

    Low capacitance through substrate via structures
    108.
    发明授权
    Low capacitance through substrate via structures 有权

    公开(公告)号：US11362018B2

    公开(公告)日：2022-06-14

    申请号：US16668296

    申请日：2019-10-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Deepak C. Pandey ,  Haitao Liu ,  Chandra Mouli

    IPC: H01L23/538 ,  H01L23/48 ,  H01L21/768 ,  H01L23/532

    Abstract: Apparatuses and methods are disclosed herein for the formation of to capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate. Wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.

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