公开(公告)号：US08254160B2

公开(公告)日：2012-08-28

申请号：US12887043

申请日：2010-09-21

申请人： Kenichi Murooka ,  Hirofumi Inoue

发明人： Kenichi Murooka ,  Hirofumi Inoue

IPC分类号： G11C11/00

CPC分类号： G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149

摘要： According to one embodiment, a semiconductor memory device includes: word lines; bit lines; an insulating film; an interlayer insulating film; and a resistance varying material. The word lines, the bit lines and the insulating film configure a field-effect transistor at each of the intersections of the word lines and the bit lines. The field-effect transistor has one of the word lines as a control electrode and one of the bit lines as a channel region. The field-effect transistor and the resistance varying material configure a memory cell having the field-effect transistor and the resistance varying material connected in parallel. Each of the bit lines includes a first surface opposing the word lines, and a second surface on an opposite side to the first surface. The resistance varying material is disposed in contact with the second surface and has a portion thereof in contact with the interlayer insulating film.

摘要翻译： 根据一个实施例，半导体存储器件包括：字线; 位线 绝缘膜; 层间绝缘膜; 和电阻变化材料。 字线，位线和绝缘膜在字线和位线的每个交点处构成场效应晶体管。 场效应晶体管具有作为控制电极的字线之一和位线之一作为沟道区。 场效应晶体管和电阻变化材料配置具有并联连接的场效应晶体管和电阻变化材料的存储单元。 每个位线包括与字线相对的第一表面和与第一表面相反的一侧上的第二表面。 电阻变化材料设置成与第二表面接触并且其一部分与层间绝缘膜接触。

公开(公告)号：US08191874B2

公开(公告)日：2012-06-05

申请号：US12280292

申请日：2007-03-06

申请人： Hirofumi Inoue ,  Hiroaki Date ,  Kazuo Ogawa

发明人： Hirofumi Inoue ,  Hiroaki Date ,  Kazuo Ogawa

IPC分类号： F16F15/36 ,  F16F9/00 ,  F16F15/03

CPC分类号： B60G11/27 ,  B60G13/14 ,  B60G15/02 ,  B60G17/015 ,  B60G17/0157 ,  B60G2202/12 ,  B60G2202/42 ,  B60G2300/60 ,  B60G2400/102 ,  B60G2400/252 ,  F16F2232/06

摘要： A vehicle suspension system including: (a) a suspension spring interconnecting a vehicle body and a wheel; (b) an actuator having an electric motor, such that the actuator is capable of generating, based on a force of the electric motor, an actuator force forcing the body and the wheel toward and away from each other, and causing the generated actuator force to act as a damping force against displacement of the body and the wheel; and (c) a control device for controlling the actuator force generated by the actuator, by controlling operation of the electric motor. The control device is capable of establishing a constant-force generating state in which the actuator force is constantly generated as a constant actuator force by the actuator with supply of an electric power thereto from a battery as an electric power source of the electric motor such that the generated constant actuator force acts in a rebound direction or a bound direction. The control device controls the constant-force generating state, based on a charge state of the battery.

摘要翻译： 一种车辆悬架系统，包括：（a）将车体和车轮相互连接的悬架弹簧; （b）具有电动机的致动器，使得所述致动器能够基于所述电动机的力产生致使所述主体和所述车轮朝向和远离彼此的致动器力，并且使所产生的致动器力 作为抵抗身体和车轮位移的阻尼力; 和（c）通过控制电动机的动作来控制由致动器产生的致动器力的控制装置。 控制装置能够建立恒力产生状态，其中致动器力通过致动器作为恒定的致动器力而始终产生，该致动器从作为电动机的电源的电池向其提供电力，使得 所产生的恒定致动器力作用在回弹方向或束缚方向上。 控制装置基于电池的充电状态来控制恒定力产生状态。

公开(公告)号：US08183671B2

公开(公告)日：2012-05-22

申请号：US13323965

申请日：2011-12-13

申请人： Shinichi Watanabe ,  Hirofumi Inoue

发明人： Shinichi Watanabe ,  Hirofumi Inoue

IPC分类号： H01L27/115 ,  H01L21/336

CPC分类号： H01L21/28123 ,  H01L29/4238

摘要： A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region and a drain region which are provided in the semiconductor substrate and spaced apart from each other in a manner to sandwich the gate electrode, both end portions of each of the source region and the drain region being offset from the device isolation insulating film in a channel width direction by a predetermined distance, and first and second gate electrode extension portions which are provided in a manner to cover both end portions of each of the source region and the drain region in a channel length direction.

公开(公告)号：US08044456B2

公开(公告)日：2011-10-25

申请号：US12540092

申请日：2009-08-12

申请人： Hiroyuki Nagashima ,  Hirofumi Inoue ,  Hideyuki Tabata ,  Masanori Komura ,  Eiji Ito

发明人： Hiroyuki Nagashima ,  Hirofumi Inoue ,  Hideyuki Tabata ,  Masanori Komura ,  Eiji Ito

IPC分类号： H01L29/792

CPC分类号： H01L27/1116 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/105 ,  H01L27/115 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

摘要： A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.

摘要翻译： 单元阵列包括其中形成存储器单元的存储单元区域和设置在存储单元区域周围的外围区域。 在存储单元区域中，第一线与第一方向平行地延伸，并且第一线在与第一方向正交的第二方向上以第一间隔重复形成。 在周边区域中，位于第（4n-3）（n是正整数）的第一线和从预定位置起的第二方向的第（4n-2）个位置中的每一个在一个上具有接触连接部分 在第一行的第一个方向的端部。 在周边区域中，位于距规定位置的第二方向（4n-1）和第4n位置的第一线的第一线在第一线的第一方向的另一端侧具有接触连接部 。 接触连接部形成为与层叠方向延伸的接触插塞接触。

公开(公告)号：US08027188B2

公开(公告)日：2011-09-27

申请号：US12325040

申请日：2008-11-28

申请人： Hiroyuki Nagashima ,  Hirofumi Inoue

发明人： Hiroyuki Nagashima ,  Hirofumi Inoue

IPC分类号： G11C11/00

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.

公开(公告)号：US07887064B2

公开(公告)日：2011-02-15

申请号：US12445235

申请日：2007-08-28

申请人： Hirofumi Inoue

发明人： Hirofumi Inoue

IPC分类号： B60G17/015

CPC分类号： B60G11/27 ,  B60G15/067 ,  B60G17/0157 ,  B60G2202/152 ,  B60G2202/42 ,  F16F15/002 ,  F16F2232/04

摘要： In a system in which an actuator force to be generated by an actuator is controlled based on a component sum that is a sum of a vibration damping component as the actuator force to be generated in a vibration damping control and a posture control component that is the actuator force to be generated in a body-posture control, a control in which the posture control component is limited so as to be not larger than a limit value is executable. The system ensures the actuator force that should be generated in the vibration damping control by limiting the posture control component, in a situation in which there is a limit in the actuator force that can be generated. Accordingly, a sufficient amount of a damping force can be generated, so that riding comfort of the vehicle and the like is prevented from being deteriorated.

摘要翻译： 在由致动器产生的致动器力基于作为在减振控制中产生的致动器力的振动阻尼分量和作为在减振控制中产生的作用力的和的分量和的控制的系统中进行控制的系统中， 在体姿控制中产生的致动器力可以执行将姿势控制部件限制为不大于限制值的控制。 在可以产生致动器力的限制的情况下，该系统通过限制姿势控制部件来确保在减振控制中产生的致动器力。 因此，能够产生足够的阻尼力，防止车辆等的乘坐舒适性恶化。

公开(公告)号：US20110032745A1

公开(公告)日：2011-02-10

申请号：US12846198

申请日：2010-07-29

申请人： Reika ICHIHARA ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue ,  Hiroshi Kanno

发明人： Reika ICHIHARA ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue ,  Hiroshi Kanno

IPC分类号： G11C11/00

CPC分类号： G11C13/0061 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092

摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.

摘要翻译： 根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。 根据本发明实施例的一个方面的非易失性半导体存储器件还包括用于选择给定的一个存储单元的控制器，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给 选择的存储单元。 擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。

公开(公告)号：US07800091B2

公开(公告)日：2010-09-21

申请号：US12108783

申请日：2008-04-24

申请人： Takeshi Kamigaichi ,  Hirofumi Inoue

发明人： Takeshi Kamigaichi ,  Hirofumi Inoue

IPC分类号： H01L29/04

CPC分类号： H01L27/2409 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147

摘要： A nonvolatile semiconductor memory device includes a first stacked structure in which a plurality of electrode layers are stacked on a substrate via insulating layers, a first resistance changing layer provided on a side surface of the first stacked structure and in contact with the first electrode layers, the first resistance changing layer having a resistance value changing on the basis of an applied voltage, a second electrode layer provided on a side surface of the first resistance changing layer, and a bit line provided on the first stacked structure and electrically connected to the second electrode layer.

摘要翻译： 非易失性半导体存储器件包括：第一堆叠结构，其中多个电极层经由绝缘层堆叠在衬底上;第一电阻改变层，设置在第一堆叠结构的侧表面上并与第一电极层接触; 所述第一电阻变化层具有基于施加电压而变化的电阻值，设置在所述第一电阻变化层的侧面上的第二电极层和设置在所述第一堆叠结构上并与所述第二电阻变化层电连接的位线 电极层。

公开(公告)号：US20100186996A1

公开(公告)日：2010-07-29

申请号：US12669416

申请日：2008-07-11

申请人： Tomokazu Umezawa ,  Tetsuo Wada ,  Hirofumi Inoue

发明人： Tomokazu Umezawa ,  Tetsuo Wada ,  Hirofumi Inoue

IPC分类号： H05K1/02 ,  C08L75/04

CPC分类号： H05K3/285 ,  C08G59/4246 ,  H01L23/293 ,  H01L2924/0002 ,  H05K2203/124 ,  Y10T428/31551 ,  Y10T428/31605 ,  Y10T428/31609 ,  H01L2924/00

摘要： The thermosetting resin composition according to the present invention includes a resin (A) containing two or more carboxyl groups and having a polyurethane structure, a strongly basic nitrogen-containing heterocyclic compound having pKa of 10.0 to 14.0 as a curing accelerator (B) and a curing agent (C). A cured product of the thermosetting resin composition is used as an insulating protective film for printed wiring boards, flexible printed wiring boards, chip-on-films, etc. The thermosetting resin composition of the invention has improved low-temperature curability and instantaneous curability, can realize tack-free property, can simultaneously realize low warpage property and electrical insulation property, does not contaminate a curing oven and the like by outgassing during heating, has a sufficient pot life, can form excellent cured products and insulating protective films, and can form solder resists and insulating protective films at low cost with good productivity.

摘要翻译： 根据本发明的热固性树脂组合物包含含有两个或更多个羧基并具有聚氨酯结构的树脂（A），作为固化促进剂（B）的pKa为10.0〜14.0的强碱性含氮杂环化合物和 固化剂（C）。 热固性树脂组合物的固化物用作印刷线路板，柔性印刷电路板，片上胶片等的绝缘保护膜。本发明的热固性树脂组合物具有改善的低温固化性和瞬时固化性， 可实现无粘性，可同时实现低翘曲性和电绝缘性，加热时除气不会污染固化炉等，具有足够的使用期限，可形成优良的固化产物和绝缘保护膜，并可 以低成本形成阻焊和绝缘保护膜，生产率高。

公开(公告)号：US20100038616A1

公开(公告)日：2010-02-18

申请号：US12540092

申请日：2009-08-12

申请人： Hiroyuki NAGASHIMA ,  Hirofumi Inoue ,  Hideyuki Tabata ,  Masanori Komura ,  Eiji Ito

发明人： Hiroyuki NAGASHIMA ,  Hirofumi Inoue ,  Hideyuki Tabata ,  Masanori Komura ,  Eiji Ito

IPC分类号： H01L47/00

CPC分类号： H01L27/1116 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/105 ,  H01L27/115 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

摘要： A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.

摘要翻译： 单元阵列包括其中形成存储器单元的存储单元区域和设置在存储单元区域周围的外围区域。 在存储单元区域中，第一线与第一方向平行地延伸，并且第一线在与第一方向正交的第二方向上以第一间隔重复形成。 在外围区域中，位于第（4n-3）（n为正整数）的第一线和从预定位置起的第二方向的第（4n-2）个位置中的每一个在一个上具有接触连接部 在第一行的第一个方向的端部。 在周边区域中，位于距规定位置的第二方向（4n-1）和第4n位置的第一线的第一线在第一线的第一方向的另一端侧具有接触连接部 。 接触连接部形成为与层叠方向延伸的接触插塞接触。