公开(公告)号：US07727708B2

公开(公告)日：2010-06-01

申请号：US12121502

申请日：2008-05-15

申请人： Matthew E. Colburn ,  Dario L. Goldfarb

发明人： Matthew E. Colburn ,  Dario L. Goldfarb

IPC分类号： G03F7/26

CPC分类号： G03F7/094 ,  G03F1/50

摘要： A method for fabricating a dual damascene structure includes providing a multi-layer photoresist stack comprising a first photoresist layer and a second photoresist layer, wherein each photoresist layer has a distinct dose-to-clear value, exposing said photoresist stack to one or more predetermined patterns of light, and developing said photo-resist layers to form a multi-tiered structure in the photo-resist layers.

摘要翻译： 一种用于制造双镶嵌结构的方法包括提供包括第一光致抗蚀剂层和第二光致抗蚀剂层的多层光致抗蚀剂层，其中每个光致抗蚀剂层具有不同的剂量至清除值，将所述光致抗蚀剂层暴露于一个或多个预定的 并且显影所述光致抗蚀剂层以在光致抗蚀剂层中形成多层结构。

公开(公告)号：US07692308B2

公开(公告)日：2010-04-06

申请号：US12256735

申请日：2008-10-23

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.

摘要翻译： 电路结构包括至少两个大致平行的导体结构，以及多个基本上水平的层介质材料层，散布着基本上水平延伸的相对较低的介电常数（低k）体积。 基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。 还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积，以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。 与不包括相对低k体积的其他可比较的微电子电路相比，基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。

公开(公告)号：US07666753B2

公开(公告)日：2010-02-23

申请号：US11622188

申请日：2007-01-11

申请人： Griselda Bonilla ,  Shyng-Tsong Chen ,  Matthew E. Colburn ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Shyng-Tsong Chen ,  Matthew E. Colburn ,  Chih-Chao Yang

IPC分类号： H01L21/76

CPC分类号： H01L23/53238 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： The embodiments of the invention provide a metal capping process for a BEOL interconnect with air gaps. More specifically an apparatus is provided comprising metal lines within a first dielectric. Metal caps are over the metal lines, wherein the metal caps contact the metal lines. In addition, air gaps are between the metal lines, wherein the air gaps are between the metal caps. A second dielectric is also provided over the bottom portion of a first dielectric, wherein a top portion of the second dielectric is over the metal caps, and wherein top portions of the first dielectric and bottom portions of the second dielectric comprise sides of the air gap. The apparatus further includes dielectric caps over the metal lines, wherein the dielectric caps contact the metal caps.

摘要翻译： 本发明的实施例提供了一种用于具有气隙的BEOL互连的金属封盖工艺。 更具体地，提供了一种包括在第一电介质内的金属线的装置。 金属盖在金属线上方，金属帽与金属线接触。 此外，气隙在金属线之间，其中气隙在金属盖之间。 第二电介质还设置在第一电介质的底部上方，其中第二电介质的顶部在金属帽之上，并且其中第二电介质的第一电介质和底部的顶部包括气隙的侧面 。 该装置还包括金属线上的电介质盖，其中介电帽与金属盖接触。

公开(公告)号：US20090081598A1

公开(公告)日：2009-03-26

申请号：US11859804

申请日：2007-09-24

申请人： Robert D. Allen ,  Matthew E. Colburn ,  Daniel P. Sanders ,  Ratnam Sooriyakumaran ,  Hoa D. Truong

发明人： Robert D. Allen ,  Matthew E. Colburn ,  Daniel P. Sanders ,  Ratnam Sooriyakumaran ,  Hoa D. Truong

IPC分类号： G03C1/73 ,  G03C5/00

CPC分类号： G03F7/0397 ,  G03F7/0757 ,  Y10S430/106 ,  Y10S430/108 ,  Y10S430/143 ,  Y10S430/168

摘要： Linear or branched functionalized polycarbosilanes having an absorbance less than 3.0 μm−1 at 193 nm and a relatively high refractive index are provided. The functionalized polycarbosilanes contain at least one pendant group that is acid labile or aqueous base soluble. Also disclosed are photoresists formulations containing the functionalized polycarbosilanes that are suitable for use in lithography, e.g., immersion lithography.

公开(公告)号：US20090072410A1

公开(公告)日：2009-03-19

申请号：US12256735

申请日：2008-10-23

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L23/52

CPC分类号： H01L21/7682 ,  H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.

摘要翻译： 电路结构包括至少两个大致平行的导体结构，以及多个基本上水平的层介质材料层，散布着基本上水平延伸的相对较低的介电常数（低k）体积。 基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。 还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积，以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。 与不包括相对低k体积的其他可比较的微电子电路相比，基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。

公开(公告)号：US20080308801A1

公开(公告)日：2008-12-18

申请号：US12193288

申请日：2008-08-18

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Michael C. Gaidis ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Michael C. Gaidis ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L23/58

CPC分类号： H01L23/576 ,  H01L21/31144 ,  H01L23/544 ,  H01L28/20 ,  H01L28/40 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.

摘要翻译： 一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机 结构纳米孔特征。 在无规纳米孔结构化中间层上形成上导电层。 上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。

公开(公告)号：US07439172B2

公开(公告)日：2008-10-21

申请号：US11623478

申请日：2007-01-16

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/7682

摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。

公开(公告)号：US20080248655A1

公开(公告)日：2008-10-09

申请号：US12143445

申请日：2008-06-20

申请人： Matthew E. Colburn ,  Dmitriy Shneyder ,  Shahab Siddiqui

发明人： Matthew E. Colburn ,  Dmitriy Shneyder ,  Shahab Siddiqui

IPC分类号： H01L21/31 ,  G03C5/00

CPC分类号： G03F7/168 ,  G03F7/325 ,  Y10S438/922 ,  Y10S977/733 ,  Y10S977/734

摘要： Methods of developing or removing a select region of block copolymer films using a polar supercritical solvent to dissolve a select portion are disclosed. In one embodiment, the polar supercritical solvent includes chlorodifluoromethane, which may be exposed to the block copolymer film using supercritical carbon dioxide (CO2) as a carrier or chlorodiflouromethane itself in supercritical form. The invention also includes a method of forming a nano-structure including exposing a polymeric film to a polar supercritical solvent to develop at least a portion of the polymeric film. The invention also includes a method of removing a poly(methyl methacrylate-b-styrene) (PMMA-b-S) based resist using a polar supercritical solvent.

摘要翻译： 公开了使用极性超临界溶剂显影或除去嵌段共聚物膜的选择区域以溶解选择部分的方法。 在一个实施方案中，极性超临界溶剂包括氯二氟甲烷，其可以使用超临界二氧化碳（CO 2 CO 2）作为载体或氯二氟乙烷本身以超临界形式暴露于嵌段共聚物膜。 本发明还包括形成纳米结构的方法，包括将聚合物膜暴露于极性超临界溶剂以形成至少一部分聚合物膜。 本发明还包括使用极性超临界溶剂除去聚（甲基丙烯酸甲酯-b-苯乙烯）（PMMA-b-S）基抗蚀剂的方法。

公开(公告)号：US07407554B2

公开(公告)日：2008-08-05

申请号：US10907688

申请日：2005-04-12

申请人： Matthew E. Colburn ,  Dmitriy Shneyder ,  Shahab Siddiqui

发明人： Matthew E. Colburn ,  Dmitriy Shneyder ,  Shahab Siddiqui

IPC分类号： B08B7/04 ,  G03F7/34

CPC分类号： G03F7/168 ,  G03F7/325 ,  Y10S438/922 ,  Y10S977/733 ,  Y10S977/734

摘要： Methods of developing or removing a select region of block copolymer films using a polar supercritical solvent to dissolve a select portion are disclosed. In one embodiment, the polar supercritical solvent includes chlorodifluoromethane, which may be exposed to the block copolymer film using supercritical carbon dioxide (CO2) as a carrier or chlorodiflouromethane itself in supercritical form. The invention also includes a method of forming a nano-structure including exposing a polymeric film to a polar supercritical solvent to develop at least a portion of the polymeric film. The invention also includes a method of removing a poly(methyl methacrylate-b-styrene) (PMMA-b-S) based resist using a polar supercritical solvent.

摘要翻译： 公开了使用极性超临界溶剂显影或除去嵌段共聚物膜的选择区域以溶解选择部分的方法。 在一个实施方案中，极性超临界溶剂包括氯二氟甲烷，其可以使用超临界二氧化碳（CO 2 CO 2）作为载体或氯二氟乙烷本身以超临界形式暴露于嵌段共聚物膜。 本发明还包括形成纳米结构的方法，包括将聚合物膜暴露于极性超临界溶剂以形成至少一部分聚合物膜。 本发明还包括使用极性超临界溶剂除去聚（甲基丙烯酸甲酯-b-苯乙烯）（PMMA-b-S）基抗蚀剂的方法。

公开(公告)号：US20080171432A1

公开(公告)日：2008-07-17

申请号：US11623478

申请日：2007-01-16

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/7682

摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of inter connect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一电介质层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。