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73 条记录 (耗时 0.021 秒)

    INTERCONNECT STRUCTURES WITH PATTERNABLE LOW-K DIELECTRICS AND METHOD OF FABRICATING SAME
    1.
    发明申请
    INTERCONNECT STRUCTURES WITH PATTERNABLE LOW-K DIELECTRICS AND METHOD OF FABRICATING SAME 有权
    具有可编程低K电介质的互连结构及其制造方法

    公开(公告)号：US20100283157A1

    公开(公告)日：2010-11-11

    申请号：US12841359

    申请日：2010-07-22

    申请人： Qinghuang Lin ,  Shyng-Tsong Chen

    发明人： Qinghuang Lin ,  Shyng-Tsong Chen

    IPC分类号： H01L23/522 ,  H01L21/768

    CPC分类号： H01L21/76808 ,  H01L21/02137 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/31 ,  H01L21/3122 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and cured low-k dielectric material located on a surface of a substrate. The at least one cured and patterned low-k material has conductively filled regions embedded therein and typically, but not always, includes Si atoms bonded to cyclic rings via oxygen atoms. The present invention also provides a method of forming such interconnect structures in which no separate photoresist is employed in patterning the patterned low-k material.

    摘要翻译： 本发明提供一种互连结构，其中使用可图案化的低k材料作为互连电介质材料。 具体而言，本发明涉及具有至少一个可构图的低k电介质的单镶嵌和双镶嵌低k互连结构。 一般来说，互连结构包括位于衬底表面上的至少一个图案化和固化的低k电介质材料。 所述至少一种固化和图案化的低k材料具有嵌入其中的导电填充区域，并且通常但不总是包括通过氧原子键合到环上的Si原子。 本发明还提供一种形成这种互连结构的方法，其中在图案化的低k材料图案中不使用单独的光致抗蚀剂。

    INTERCONNECT STRUCTURES WITH PATTERNABLE LOW-K DIELECTRICS AND METHOD OF FABRICATING SAME
    3.
    发明申请
    INTERCONNECT STRUCTURES WITH PATTERNABLE LOW-K DIELECTRICS AND METHOD OF FABRICATING SAME 有权
    具有可编程低K电介质的互连结构及其制造方法

    公开(公告)号：US20090079075A1

    公开(公告)日：2009-03-26

    申请号：US11858624

    申请日：2007-09-20

    申请人： Qinghuang Lin ,  Shyng-Tsong Chen

    发明人： Qinghuang Lin ,  Shyng-Tsong Chen

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L21/02137 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/31 ,  H01L21/3122 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and cured low-k dielectric material located on a surface of a substrate. The at least one cured and patterned low-k material has conductively filled regions embedded therein and typically, but not always, includes Si atoms bonded to cyclic rings via oxygen atoms. The present invention also provides a method of forming such interconnect structures in which no separate photoresist is employed in patterning the patterned low-k material.

    摘要翻译： 本发明提供一种互连结构，其中使用可图案化的低k材料作为互连电介质材料。 具体而言，本发明涉及具有至少一个可构图的低k电介质的单镶嵌和双镶嵌低k互连结构。 一般来说，互连结构包括位于衬底表面上的至少一个图案化和固化的低k电介质材料。 所述至少一种固化和图案化的低k材料具有嵌入其中的导电填充区域，并且通常但不总是包括通过氧原子键合到环上的Si原子。 本发明还提供一种形成这种互连结构的方法，其中在图案化的低k材料图案中不使用单独的光致抗蚀剂。

    METHOD OF FORMING AN INTERCONNECT STRUCTURE
    4.
    发明申请
    METHOD OF FORMING AN INTERCONNECT STRUCTURE 审中-公开
    形成互连结构的方法

    公开(公告)号：US20080146029A1

    公开(公告)日：2008-06-19

    申请号：US12033943

    申请日：2008-02-20

    申请人： Heidi Lee Baks ,  Shyng-Tsong Chen ,  Timothy Joseph Dalton ,  Nicholas Colvin Masi Fuller

    发明人： Heidi Lee Baks ,  Shyng-Tsong Chen ,  Timothy Joseph Dalton ,  Nicholas Colvin Masi Fuller

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76811

    摘要： A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the hardmask and organo-silicate glass layers using a combination of plasma etch and plasma photoresist removal processes and performing one or more additional plasma etch processes that do not include oxygen containing species to etch the openings to depths required for forming the damascene interconnect structures and to remove any organo-silicate material damaged by the combination of plasma etch and plasma photoresist removal processes.

    摘要翻译： 在有机硅酸盐玻璃层中形成镶嵌互连结构而不会损坏有机硅酸盐玻璃材料的方法。 该方法包括在有机硅酸盐玻璃层上形成硬掩模层堆叠，使用等离子体蚀刻和等离子体光致抗蚀剂去除方法的组合在硬掩模和有机硅酸盐玻璃层中限定开口，并执行一个或多个额外的等离子体蚀刻工艺 不包括含氧物质，以将开口蚀刻到形成镶嵌互连结构所需的深度，并除去由等离子体蚀刻和等离子体光致抗蚀剂去除工艺的组合损坏的任何有机硅酸盐材料。

    Method of making a semiconductor structure with a plating enhancement layer
    5.
    发明授权
    Method of making a semiconductor structure with a plating enhancement layer 有权
    制造具有电镀增强层的半导体结构的方法

    公开(公告)号：US07341948B2

    公开(公告)日：2008-03-11

    申请号：US11306930

    申请日：2006-01-17

    申请人： Shom Ponoth ,  Steven Shyng-Tsong Chen ,  John Anthony Fitzsimmons ,  Terry Allen Spooner

    发明人： Shom Ponoth ,  Steven Shyng-Tsong Chen ,  John Anthony Fitzsimmons ,  Terry Allen Spooner

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76873 ,  H01L21/7688 ,  H01L2221/1089

    摘要： Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a seed layer into the pattern formed by the ILD and PEL, and then plating copper on the seed layer. The PEL serves to decrease the resistance across the wafer so to facilitate the plating of the copper. The PEL preferably is an optically transparent and conductive layer.

    摘要翻译： 公开了一种半导体结构的制造方法，其特征在于，在半导体层上形成层间电介质层（ILD）层，在ILD上形成导电性电镀增强层（PEL），图案化ILD和PEL， 进入由ILD和PEL形成的图案，然后在种子层上镀铜。 PEL用于降低晶片上的电阻，以便于镀铜。 PEL优选是光学透明且导电的层。

    METAL RESISTOR, RESISTOR MATERIAL AND METHOD
    6.
    发明申请
    METAL RESISTOR, RESISTOR MATERIAL AND METHOD 有权
    金属电阻器，电阻材料和方法

    公开(公告)号：US20070293000A1

    公开(公告)日：2007-12-20

    申请号：US11420121

    申请日：2006-06-16

    申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Shyng-Tsong Chen

    发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Shyng-Tsong Chen

    IPC分类号： H01L21/338

    CPC分类号： H01L29/86 ,  H01L23/5228 ,  H01L2924/0002 ,  H04W36/08 ,  H04W88/08 ,  H04W88/18 ,  H01L2924/00

    摘要： A metal resistor and resistor material and method of forming the metal resistor are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W). The method is less complex than conventional processes, allows control of the resistance by the amount of infusion material infused, and is compatible with conventional BEOL processes.

    摘要翻译： 公开了一种金属电阻器和电阻器材料以及形成金属电阻器的方法。 金属电阻器可以包括从由以下组成的组中输入的输入金属：铜（Cu），其输入硅（Si），氮（N 2/2），碳（C），钽（ Ta），钛（Ti）和钨（W），以及输入硅（Si），氮（N 2/2），碳（C），钽（Ta），钛 （Ti）和钨（W）。 该方法比常规方法复杂得多，允许通过灌注材料的量控制电阻，并且与传统的BEOL方法兼容。