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101.发明授权DCBST with ICBI mechanism to maintain coherency of bifurcated data and instruction caches 失效DCBST与ICBI机制保持分叉数据和指令高速缓存的一致性公开(公告)号：US06178484B1
公开(公告)日：2001-01-23
申请号：US09024585
申请日：1998-02-17
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0811
摘要： Depending on a processor or instruction mode, a data cache block store (dcbst) or equivalent instruction is treated differently. A coherency maintenance mode for the instruction, in which the instruction is utilized to maintain coherency between bifurcated data and instruction caches, may be entered by setting bits in a processor register or by setting hint bits within the instruction. In the coherency maintenance mode, the instruction both pushes modified data to system memory and invalidates the cache entry in instruction caches. Subsequent instruction cache block invalidate (icbi) or equivalent instructions targeting the same cache location are no-oped when issued by a processor following a data cache block store or equivalent instruction executed in coherency maintenance mode. Execution of the data cache clock store instruction in coherency maintenance mode results in a novel system bus operation being initiated on the system bus. The bus operation directs other devices having bifurcated data and instruction caches to clean the specified cache entry in their data cache to at least the point of instruction/data cache coherency and invalidate the specified cache entry in their instruction cache. When repeatedly employed in sequence to write one or more pages of data to system memory, the mechanism for maintaining coherency saves processor cycles and reduces both address and data bus traffic.
摘要翻译： 根据处理器或指令模式，数据高速缓存块存储（dcbst）或等效指令的处理方式不同。 可以通过设置处理器寄存器中的位或通过在指令内设置提示位来输入用于指令用于维持分支数据和指令高速缓存之间的一致性的指令的一致性维护模式。 在相干维护模式下，指令将修改的数据推送到系统存储器，并使指令高速缓存中的高速缓存条目无效。 随后指令高速缓存块无效（icbi）或针对同一高速缓存位置的等效指令在由数据高速缓存块存储器执行的处理器发出或在相干性维护模式下执行的等效指令时不会执行。 在一致性维护模式下执行数据高速缓存时钟存储指令导致在系统总线上启动新颖的系统总线操作。 总线操作指示具有分叉数据和指令高速缓存的其他设备将其数据高速缓存中的指定高速缓存条目清理为至少指令/数据高速缓存一致性点，并使其指令高速缓存中指定的高速缓存条目无效。 当重复按顺序将一个或多个数据页写入系统存储器时，用于维持一致性的机制节省了处理器周期，并减少了地址和数据总线流量。
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公开(公告)号：US06173371B2
公开(公告)日：2001-01-09
申请号：US08834113
申请日：1997-04-14
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A method of managing and speculatively issuing architectural operations in a computer system. A first architectural operation is snooped and translated into a plurality of granular architectural operations to effect a large-scale architectural operation. The first architectural operation can be a first cache instruction directed to a memory block, and a plurality of cache instructions are issued which are directed to memory blocks contained in a page associated with the memory block. The granular architectural operations are transmitted to a processor bus of the computer system. A processor bus history table may be used to store a record of the large-scale architectural operation. The history table then can filter out any later architectural operation that is subsumed by the large-scale architectural operation. The history table monitors the processor bus to ensure that the large-scale architectural operations recorded in the table are still valid.
摘要翻译： 一种在计算机系统中管理和推测性地发布架构操作的方法。 第一个架构操作被窥探并转换成多个细粒度的架构操作，以实现大规模的架构操作。 第一架构操作可以是针对存储器块的第一高速缓存指令，并且发出指向包含在与存储器块相关联的页面中的存储器块的多个高速缓存指令。 粒度结构操作被传送到计算机系统的处理器总线。 处理器总线历史表可以用于存储大型建筑操作的记录。 历史表然后可以过滤掉大型建筑操作所包含的任何后来的建筑操作。 历史表监视处理器总线，以确保表中记录的大型架构操作仍然有效。
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103.发明授权Forward progress on retried snoop hits by altering the coherency state of a local cache 失效通过更改本地缓存的一致性状态来重试侦听命中的进展
公开(公告)号：US6138218A
公开(公告)日：2000-10-24
申请号：US24616
申请日：1998-02-17
CPC分类号： G06F12/0833 , G06F12/0811
摘要： When a device snooping the system bus of a multiprocessor system detects an operation requesting data which is resident within a local memory in a coherency state requiring the data to be sourced from the device, the device attempts a intervention. If the intervention is impeded by a second device asserting a retry, the device sets a flag to provide historical information regarding the failed intervention. On a subsequent snoop hit to the same cache location, if the device again asserts an intervention and the snooped operation is again retried, the device undertakes an action to alter the coherency state of the requested cache item towards an ultimate coherency state expected to be the result of the original operation requesting the cache item. In the case where the requested cache item includes modified data resident in the device's local memory, the action may include a push operation writing the requested cache item to system memory. This operation may be snooped by other devices from the system bus to update their local memories. In the case where the requested cache item includes data in a coherency state other than the modified state, the action may include simply altering the coherency state to a shared or invalid state.
摘要翻译： 当监视多处理器系统的系统总线的设备检测到需要数据来自设备的一致性状态下请求驻留在本地存储器内的数据的操作时，设备尝试干预。 如果介入被第二个设备阻止重试，设备将设置一个标志来提供有关故障干预的历史信息。 在随后的窥探命中到相同的高速缓存位置时，如果设备再次断言干预并且再次重试被窥探的操作，则设备进行动作以将所请求的高速缓存项目的一致性状态改变为预期为最终相关性的最终一致性状态 请求缓存项目的原始操作的结果。 在请求的高速缓存项目包括驻留在设备的本地存储器中的修改数据的情况下，该动作可以包括将所请求的高速缓存项目写入系统存储器的推送操作。 该操作可能被其他设备从系统总线窥探以更新其本地存储器。 在所请求的高速缓存项目包括除修改状态之外的一致性状态的数据的情况下，该动作可以包括简单地将一致性状态改变为共享状态或无效状态。
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104.发明授权Method and apparatus for layering cache and architectural specific functions to expedite multiple design 失效用于分层缓存和架构特定功能的方法和装置，以加快多重设计
公开(公告)号：US6032226A
公开(公告)日：2000-02-29
申请号：US834115
申请日：1997-04-14
CPC分类号： G06F12/0888
摘要： Cache and architectural specific functions within a cache controller are layered and provided with generic interfaces, isolating the complexities of each and allowing the overall functionality to be further divided into distinct, largely autonomous functional units. Each functional unit handles a certain type of operation and may be easily replicated or removed from the design to provide a number of cache designs with varied price and performance.
摘要翻译： 高速缓存控制器中的缓存和架构特定功能被分层并提供通用接口，隔离每个接口的复杂性，并允许将整体功能进一步分为不同的，主要是自主的功能单元。 每个功能单元处理某种类型的操作，并且可以容易地从设计中复制或移除，以提供具有不同价格和性能的多个高速缓存设计。
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105.发明授权Precise synchronization mechanism for SMP system buses using tagged snoop operations to avoid retries 失效SMP系统总线的精确同步机制，使用标记的窥探操作来避免重试
公开(公告)号：US6029204A
公开(公告)日：2000-02-22
申请号：US815648
申请日：1997-03-13
CPC分类号： G06F9/52
摘要： A method of synchronizing an initiating processing unit in a multi-processor computer system with other processing units in the system, by assigning a unique tag for each processing unit, and issuing synchronization messages which include the unique tag of an initiating processing unit. The processing units each have a snoop queue for receiving snoop operations and corresponding tags associated with instructions issued by an initiating processing unit, and the processors examine their respective snoop queues to determine whether any snoop operation in those queues has a tag which is the unique tag of the initiating processing unit. A retry message is sent to the initiating processing unit from any of the other processing units which determine that a snoop operation in a snoop queue has a tag which is the unique tag of the initiating processing unit. In response to the retry message, the initiating processing unit re-issues the synchronization message, and the other processors re-examine their respective snoop queues, in response to the re-issuing of the synchronization message, to determine whether any snoop operation in those queues still has a tag which is the unique tag of the initiating processing unit.
摘要翻译： 一种将多处理器计算机系统中的发起处理单元与系统中的其他处理单元同步的方法，通过为每个处理单元分配唯一标签，以及发出包括发起处理单元的唯一标签的同步消息。 处理单元各自具有用于接收窥探操作的窥探队列和与由发起处理单元发出的指令相关联的对应标签，并且处理器检查它们各自的窥探队列以确定这些队列中的任何窥探操作是否具有作为唯一标签的标签 的启动处理单元。 重试消息从确定窥探队列中的窥探操作具有作为发起处理单元的唯一标签的标签的任何其他处理单元发送到发起处理单元。 响应于重试消息，发起处理单元重新发布同步消息，并且其他处理器响应于重发同步消息而重新检查其相应的窥探队列，以确定是否有任何窥探操作 队列仍然具有作为启动处理单元的唯一标签的标签。
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106.发明授权Dual associative-cache directories allowing simultaneous read operation using two buses with multiplexors, address tags, memory block control signals, single clock cycle operation and error correction 失效双重关联缓存目录允许使用两个总线同时读操作，多路复用器，地址标签，存储块控制信号，单时钟周期操作和纠错
公开(公告)号：US6023746A
公开(公告)日：2000-02-08
申请号：US839558
申请日：1997-04-14
CPC分类号： G11C29/76 , G06F12/0846
摘要： A method of accessing values stored in a cache used by a processor of a computer system, whereby two read operations may occur simultaneously is disclosed. Memory blocks from a memory device are loaded into respective cache lines of the cache, and address tags associated with the memory blocks are written into two redundant cache directories of the cache. Thereafter, a first memory block can be read from the cache using the first cache directory, while a second memory block is simultaneously read from the cache using the second cache directory. The cache can have a single cache entry array, or two (redundant) cache entry arrays connected respectively to the two cache directories. If an error occurs when examining a particular address tag in one cache directory, then a redundant address tag can be substituted for the particular address tag by examining a corresponding line of the other cache directory.
摘要翻译： 公开了存储在由计算机系统的处理器使用的高速缓存中的值的方法，由此可以同时发生两个读取操作。 来自存储器件的存储器块被加载到高速缓存的相应高速缓存行中，并且与存储块相关联的地址标签被写入高速缓存的两个冗余高速缓存目录中。 此后，可以使用第一高速缓存目录从高速缓存读取第一存储器块，同时使用第二高速缓存目录从高速缓存同时读取第二存储器块。 高速缓存可以具有单个高速缓存条目数组或两个（冗余）高速缓存条目数组，分别连接到两个高速缓存目录。 如果在检查一个缓存目录中的特定地址标签时发生错误，则可以通过检查另一个缓存目录的相应行来替代特定地址标签的冗余地址标签。
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107.发明授权
公开(公告)号：US5978871A
公开(公告)日：1999-11-02
申请号：US834114
申请日：1997-04-14
CPC分类号： G06F12/0893 , G06F13/1668
摘要： Cache and architectural specific functions within a cache controller are layered to permit complex operations to be split into equivalent simple operations. Architectural variants of basic operations may thus be devolved into distinct cache and architectural operations and handled separately. The logic supporting the complex operations may thus be simplified and run faster.
摘要翻译： 高速缓存控制器中的缓存和架构特定功能被分层，以允许将复杂操作分成等效的简单操作。 因此，基础操作的架构变体可以被分配到不同的缓存和架构操作中并分开处理。 因此，支持复杂操作的逻辑可以被简化并且运行得更快。
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公开(公告)号：US5958068A
公开(公告)日：1999-09-28
申请号：US839554
申请日：1997-04-14
CPC分类号： G06F12/126 , G06F12/0802 , G11C29/846 , G06F2212/1032
摘要： A method of bypassing defects in a cache used by a processor of a computer system. A repair mask has an array of bit fields corresponding to cache lines in the cache, and when a particular cache line in the cache is identified as being defective, a corresponding bit field in the repair mask array is set to indicate that the particular cache line is defective, and further access to the defective cache line is prevented, based on the corresponding bit field in the repair mask array. The repair mask can be used to prevent the defective cache line from ever resulting in a cache hit, and to prevent the defective cache line from ever being chosen as a victim for cache replacement. Using a set associative cache, the defective cache line is thereby effectively removed from its respective congruence class. This approach allows the cache to use all non-defective cache lines without any cache lines being reserved for redundancy.
摘要翻译： 绕过由计算机系统的处理器使用的高速缓存中的缺陷的方法。 修复掩模具有对应于高速缓存中的高速缓存行的位字段阵列，并且当高速缓存中的特定高速缓存行被识别为有缺陷时，修复掩码阵列中的相应位字段被设置为指示特定高速缓存行 基于修复掩码阵列中的相应位字段，防止对缺陷高速缓存线的进一步访问。 可以使用修复掩码来防止有缺陷的高速缓存线从不导致高速缓存命中，并防止有缺陷的高速缓存行被选为高速缓存替换的受害者。 使用集合关联高速缓存，从而有效地从有缺陷的高速缓存行中删除其相应的一致等级。 这种方法允许高速缓存使用所有无缺陷高速缓存行，而没有为冗余保留任何高速缓存行。
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109.发明授权Multiple cache directories for non-arbitration concurrent accessing of a cache memory 失效多个缓存目录，用于缓存内存的非仲裁并发访问
公开(公告)号：US5943686A
公开(公告)日：1999-08-24
申请号：US834492
申请日：1997-04-14
CPC分类号： G06F12/0831 , G06F12/0846
摘要： A method of accessing a cache used by a processor of a computer system, to eliminate arbitration logic which would otherwise be required to handle operations from multiple snooping devices. A plurality of cache directories are provided in the cache, respectively connected directly to a plurality of snooping devices using a plurality of interconnects. An operation from a given snooping device is then handled by using a respective cache directory to issue a response to a respective interconnect. For example, a first cache directory may be connected to a first interconnect on a processor side of the cache, and a second cache directory may be connected to a second interconnect on a system bus side of the cache. This construction allows handling of operations from multiple snooping devices without having to use critical path arbitration logic. Furthermore, this construction allows for improved cache access due to the physical placement of the multiple cache directories.
摘要翻译： 访问由计算机系统的处理器使用的高速缓存的方法，以消除否则将需要来处理来自多个窥探设备的操作的仲裁逻辑。 高速缓存中提供多个高速缓存目录，分别使用多个互连直接连接到多个窥探装置。 然后，通过使用相应的缓存目录来对相应的互连进行响应来处理来自给定窥探设备的操作。 例如，第一高速缓存目录可以连接到高速缓存的处理器侧上的第一互连，并且第二高速缓存目录可以连接到高速缓存的系统总线侧上的第二互连。 这种结构允许处理来自多个窥探设备的操作，而不必使用关键路径仲裁逻辑。 此外，这种结构允许由于多个高速缓存目录的物理放置而改进的高速缓存访问。
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110.发明授权Cache intervention from only one of many cache lines sharing an unmodified value 失效缓存干预只能从许多缓存行之一共享一个未修改的值
公开(公告)号：US5940856A
公开(公告)日：1999-08-17
申请号：US837516
申请日：1997-04-14
CPC分类号： G06F12/0831
摘要： A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into at least two caches, the caches are marked as containing shared, unmodified copies of the value and, when a requesting processing unit issues a message indicating that it desires to read the value, a given one of the caches transmits a response indicating that the given cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The cache then sources the value to an interconnect which is connected to the requesting processing unit. The system memory detects the message and would normally source the value, but the response informs the memory device that the value is to be sourced by the cache instead. Since the cache latency can be much less than the memory latency, the read performance can be substantially improved with this new protocol.
摘要翻译： 公开了一种改善与多处理器计算机系统中的读取类型操作相关联的存储器延迟的方法。 在将值（数据或指令）从系统存储器加载到至少两个高速缓存中之后，高速缓存被标记为包含值的未修改的共享副本，并且当请求处理单元发出指示期望读取值的消息时 ，给定的一个高速缓存发送指示给定高速缓存可以输出该值的响应。 该响应响应于来自连接到请求处理单元的互连的高速缓存窥探消息而被发送。 响应由系统逻辑检测并从系统逻辑转发到请求处理单元。 高速缓存然后将该值输出到连接到请求处理单元的互连。 系统内存检测到该消息，并且通常会发送该值，但响应通知存储设备该值将由缓存提供。 由于缓存延迟可能远小于内存延迟，因此可以通过此新协议大大提高读取性能。
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