公开(公告)号：US20160148697A1

公开(公告)日：2016-05-26

申请号：US14849257

申请日：2015-09-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/14 ,  G11C16/08

CPC classification number: G11C16/14 ,  G11C5/025 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C16/0433 ,  G11C16/08

Abstract: A non-volatile memory device includes a matrix memory plane with columns of memory words respectively formed on each row of the memory plane by groups of memory cells and control elements respectively associated with the memory words of each row. At least some of the control elements associated with the memory words of the corresponding row form at least one control block of B control elements disposed next to one another, adjacent to a memory block containing the B memory words disposed next to one another and associated with these B control elements, a first electrically-conducting link connecting one of the B control elements to all the control electrodes of the state transistors of the corresponding group of memory cells and B-1 second electrically-conducting link(s) respectively connecting the B-1 control element(s) to all the control electrodes of the state transistors of the B-1 corresponding group(s) of memory cells.

Abstract translation: 非易失性存储器件包括矩阵存储器平面，其中存储器列的列分别在存储器平面的每一行上由存储器单元组和分别与每行的存储器字相关联的控制元件组组成。 与相应行的存储器字相关联的至少一些控制元件形成彼此相邻布置的B个控制元件的至少一个控制块，与包含彼此相邻布置的B存储器字的存储块相邻， 这些B控制元件，将B个控制元件中的一个连接到相应组的存储单元的状态晶体管的所有控制电极的第一导电链路和分别连接B的B-1个第二导电链路 -1个控制元件连接到存储器单元的B-1个相应组的状态晶体管的所有控制电极。

公开(公告)号：US09202568B2

公开(公告)日：2015-12-01

申请号：US14282857

申请日：2014-05-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G06F12/02 ,  G11C14/00 ,  G11C7/10 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C14/0063 ,  G11C7/1042 ,  G11C16/08 ,  G11C16/10

Abstract: A method for writing data into an EEPROM connected to an I2C bus, wherein the data to be written is transmitted in frames having a size corresponding to the size of a physical half-page of the memory. The programming of a data page in the memory is performed while another page is being received.

Abstract translation: 一种将数据写入连接到I2C总线的EEPROM的方法，其中要写入的数据以具有与存储器的物理半页大小对应的大小的帧传输。 在接收另一个页面的同时执行存储器中的数据页面的编程。

公开(公告)号：US20140369120A1

公开(公告)日：2014-12-18

申请号：US14298264

申请日：2014-06-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C14/00

CPC classification number: G11C14/0063 ,  G11C16/10

Abstract: A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage.

Abstract translation: 存储器件包括至少一个具有第一SRAM型元件存储器单元的存储器单元，所述第一SRAM型元件存储器单元具有彼此交叉耦合的两个反相器和两组，每个具有至少一个非易失性基本存储器单元。 两组的非易失性基本存储单元首先通过可控制的互连级耦合到电源端子，其次耦合到两个反相器的输出端和输入端。

公开(公告)号：US20140369119A1

公开(公告)日：2014-12-18

申请号：US14296014

申请日：2014-06-04

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/04 ,  G11C14/00 ,  G11C16/20

CPC classification number: G11C16/0408 ,  G11C11/404 ,  G11C14/0018 ,  G11C14/0063 ,  G11C16/20

Abstract: A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable interconnection stage that can be controlled by a control signal external to the memory cell. The nonvolatile elementary memory cell and the controllable interconnection stage are connected to one another. The floating gate transistor of the nonvolatile memory cell is controllable to be turned off when a data item stored in the elementary SRAM-type cell is programmed into the nonvolatile elementary cell.

Abstract translation: 存储器件包括具有基本SRAM型单元的存储单元和耦合在供电端和基本SRAM型单元之间的基本模块。 基本模块具有包括浮栅晶体管的单个非易失性EEPROM单元存储单元。 基本模块还具有可控制的互连级，其可以由存储器单元外部的控制信号控制。 非易失性基本存储单元和可控互连级彼此连接。 当存储在基本SRAM型单元中的数据项被编程到非易失性单元中时，非易失性存储单元的浮置栅晶体管被控制为截止。