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118 条记录 (耗时 0.052 秒)

    Processor, compiler and compilation method
    101.
    发明授权
    Processor, compiler and compilation method 有权
    处理器，编译器和编译方法

    公开(公告)号：US07761692B2

    公开(公告)日：2010-07-20

    申请号：US11452282

    申请日：2006-06-14

    申请人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

    发明人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

    IPC分类号： G06F9/38 ,  G06F9/45

    CPC分类号： G06F9/3853 ,  G06F9/30072 ,  G06F9/3822

    摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

    摘要翻译： 为了克服有条件执行的指令如果不满足条件而被执行为无操作指令的问题，导致硬件的利用效率差并且降低了有效性能，则处理器解码大于 提供的计算单元的数量并且在执行阶段之前用指令发布控制部分判断其执行条件，条件为假的指令被无效，并且分配后续的有效指令，使得有效地使用计算单元（硬件）。 编译器执行调度，使得执行条件为真的指令数量不超过硬件的并行度的上限。 在每个周期上平行布置的指令数可能超过硬件的并行程度。

    Processor, compiler and compilation method
    105.
    发明申请
    Processor, compiler and compilation method 有权

    公开(公告)号：US20060242387A1

    公开(公告)日：2006-10-26

    申请号：US11452282

    申请日：2006-06-14

    申请人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

    发明人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3853 ,  G06F9/30072 ,  G06F9/3822

    摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

    Partial enabling of functional unit based on data and size pair in register
    108.
    发明授权
    Partial enabling of functional unit based on data and size pair in register 失效
    基于数据和尺寸对的功能单元的部分启用

    公开(公告)号：US06802017B1

    公开(公告)日：2004-10-05

    申请号：US09606091

    申请日：2000-06-29

    申请人： Shuichi Takayama ,  Nobuo Higaki ,  Masato Suzuki

    发明人： Shuichi Takayama ,  Nobuo Higaki ,  Masato Suzuki

    IPC分类号： G06F132

    CPC分类号： G06F9/3016 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30167 ,  G06F9/30192 ,  Y02D10/171

    摘要： An SZ (size information) section is provided for each of registers that make up a register file. Suppose an instruction decoded requests that operand data of a particular size be loaded from a RAM into the register file or that immediate operand data of a particular size be transferred to the register file. Then, the size information of the operand data will be retained in the SZ section. The instruction decoded may also be an arithmetic and logical operation instruction requesting that operand data in the register file be referred to or an instruction requesting that the operand data be stored from the register file into the RAM. In such a case, the size information will be read out from the SZ section of the register file and only parts of various components constituting manipulation means (like ALU), which have been specified by the size information, will be enabled. As a result, the power, which is usually dissipated by a processor handling data of multiple sizes, can be cut down effectively.

    摘要翻译： 为构成寄存器文件的每个寄存器提供SZ（大小信息）部分。 假设解码的指令请求将特定大小的操作数数据从RAM加载到寄存器文件中，或者特定大小的立即操作数数据被传送到寄存器文件。 然后，操作数数据的大小信息将保留在SZ部分。 所解码的指令还可以是请求将寄存器文件中的操作数数据参考的算术和逻辑操作指令，或者请求将操作数数据从寄存器文件存储到RAM中的指令。 在这种情况下，大小信息将从寄存器文件的SZ部分读出，并且只有由尺寸信息指定的构成操作装置的各种部件（如ALU）的部分将被使能。 结果，可以有效地削减通常由处理多种尺寸的数据的处理器耗散的功率。

    Program conversion apparatus for constant reconstructing VLIW processor
    109.
    发明授权
    Program conversion apparatus for constant reconstructing VLIW processor 有权
    用于恒定重建VLIW处理器的程序转换装置

    公开(公告)号：US06367067B1

    公开(公告)日：2002-04-02

    申请号：US09143269

    申请日：1998-08-28

    申请人： Kensuke Odani ,  Akira Tanaka ,  Shuichi Takayama ,  Ryoichiro Koshimura

    发明人： Kensuke Odani ,  Akira Tanaka ,  Shuichi Takayama ,  Ryoichiro Koshimura

    IPC分类号： G06F945

    CPC分类号： G06F9/30167 ,  G06F8/445 ,  G06F8/447 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3822 ,  G06F9/3832 ,  G06F9/3853

    摘要： A program conversion apparatus includes: the constant division unit 12 for specifying instructions in the serial assembler code 42 that use large constants which cannot be arranged within the operation fields of object VLIWs and for dividing the specified instructions into divided constant use instructions for storing pieces of the large constants into the specialized constant buffer 107 of a VLIW processor and divided constant use instructions for performing operations using the stored constants; the dependence graph generation unit 20 for generating a dependence graph based on the execution order of each instruction in the serial assembler code 42 after the division process by the constant division unit 12; and the instruction relocation unit 21 for relocating the instructions according to the dependence graph to generate parallel assembler code.

    摘要翻译： 一种程序转换装置，包括：常数分割单元12，用于指定串行汇编代码42中使用大量常数的指令，该常数不能排列在对象VLIW的操作区域内，并用于将指定指令划分成分开的常数使用指令， VLIW处理器的专用常数缓冲器107中的大常数和用于使用存储的常数执行操作的分开的常数使用指令; 依赖图生成单元20，用于通过常数分割单元12的分割处理之后，基于串行汇编代码42中的每个指令的执行顺序生成依赖图; 以及用于根据依赖图重新定位指令的指令重定位单元21，以生成并行汇编代码。

    Constant reconstruction processor that supports reductions in code size and processing time
    110.
    发明授权
    Constant reconstruction processor that supports reductions in code size and processing time 失效
    恒定重建处理器，支持缩小代码大小和处理时间

    公开(公告)号：US06209080B1

    公开(公告)日：2001-03-27

    申请号：US09124335

    申请日：1998-07-29

    申请人： Taketo Heishi ,  Nobuo Higaki ,  Akira Tanaka ,  Tetsuya Tanaka ,  Shuichi Takayama ,  Kensuke Odani ,  Shinya Miyaji

    发明人： Taketo Heishi ,  Nobuo Higaki ,  Akira Tanaka ,  Tetsuya Tanaka ,  Shuichi Takayama ,  Kensuke Odani ,  Shinya Miyaji

    IPC分类号： G06F930

    CPC分类号： G06F9/30167 ,  G06F9/30163 ,  G06F9/383 ,  G06F9/3853

    摘要： A processor for executing operations based on instructions includes an operation constant register 361, a branching constant register 362, a decoding unit 20 for decoding an instruction stored in an instruction register 10, a constant register control unit 32, and an execution unit 30. When the decoding unit 20 finds that the instruction includes a constant to be stored in the branching constant register 362, the constant register control unit 32 shifts a present value in the branching constant register 362 and inserts the constant to be stored, thereby storing a new constant in the branching constant register 362. When the decoding unit 20 finds that a constant is to be stored in the operation constant register 361, the constant register control unit 32 shifts the present value in the operation constant register 361 and inserts the constant to be stored, thereby storing a new constant in the operation constant register 361. When the decoding unit 20 finds that the instruction includes a branch operation, the execution unit 30 executes the branch operation using the constant stored in the branching constant register 362. When the decoding unit 20 finds that the instruction includes an arithmetic operation, the execution unit 30 executes the arithmetic operation using the constant stored in the operation constant register 361.

    摘要翻译： 用于基于指令执行操作的处理器包括操作常数寄存器361，分支常数寄存器362，用于解码存储在指令寄存器10中的指令的解码单元20，常数寄存器控制单元32和执行单元30.当 解码单元20发现指令包括要存储在分支常数寄存器362中的常数，常数寄存器控制单元32移位分支常数寄存器362中的当前值并插入要存储的常数，从而存储新常数 在分支常数寄存器362中。当解码单元20发现将常数存储在操作常数寄存器361中时，常数寄存器控制单元32移动操作常数寄存器361中的当前值，并插入要存储的常数 ，从而在操作常数寄存器361中存储新常数。当解码单元20发现指令包括时 分支操作，执行单元30使用存储在分支常数寄存器362中的常数来执行分支操作。当解码单元20发现指令包括算术运算时，执行单元30使用存储在 操作常数寄存器361。