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    Method for reducing uncorrectable errors of a memory device regarding error correction code, and associated memory device and controller thereof
    101.
    发明授权
    Method for reducing uncorrectable errors of a memory device regarding error correction code, and associated memory device and controller thereof 有权
    用于减少存储器件关于纠错码的不可校正误差的方法，以及相关联的存储器件及其控制器

    公开(公告)号：US08631310B2

    公开(公告)日：2014-01-14

    申请号：US13942724

    申请日：2013-07-16

    Applicant: Silicon Motion Inc.

    Inventor： Tsung-Chieh Yang

    IPC: G06F11/08

    CPC classification number: G06F11/187 ,  G06F11/1048 ,  G06F11/1479

    Abstract: A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any uncorrectable error in order to determine whether to output the majority vote data as data of the address. For example, the method further includes: within the data read at different times at the same address, temporarily storing all of the data except for data of a last time into buffering regions/buffers, respectively, with the majority vote data being temporarily stored into a second buffering region/buffer to utilize a latest generated portion within the majority vote data to replace a latest retrieved portion within data in the second buffering region/buffer. An associated memory device and the controller thereof are further provided.

    Abstract translation: 一种用于减少存储器件关于纠错码（ECC）的不可校正错误的方法，包括：根据在同一地址的不同时间读取的数据执行多数投票，以便产生对应于地址的多数投票数据; 并且检查多数投票数据是否具有任何不可校正的错误，以便确定是否输出多数投票数据作为地址的数据。 例如，该方法还包括：在相同地址的不同时间读取的数据内，分别将除最后时间的数据之外的所有数据临时存储到缓冲区域/缓冲器中，将多数投票数据临时存储到 第二缓冲区域/缓冲器，以利用多数投票数据中的最新生成部分来替换第二缓冲区域/缓冲器中的数据内的最新检索部分。 还提供了一种相关联的存储器件及其控制器。

    MEMORY DEVICE CONTROL METHOD AND ASSOCIATED APPARATUS
    102.
    发明申请
    MEMORY DEVICE CONTROL METHOD AND ASSOCIATED APPARATUS 有权

    公开(公告)号：US20250077418A1

    公开(公告)日：2025-03-06

    申请号：US18810473

    申请日：2024-08-20

    Applicant: Silicon Motion, Inc.

    Inventor： Tsung-Chieh Yang

    IPC: G06F12/02

    Abstract: A control method of a memory device includes: reading and decoding first data of a first chunk, wherein the first chunk is located in a first data page of a super data page, and the super data page includes multiple data pages respectively located in multiple data planes; in response to the first chunk failing to be decoded, obtaining data of multiple corresponding chunks of the first chunk, wherein the multiple corresponding chunks are located in other data pages of the super data page; and in response to all of the data in the multiple corresponding chunks not being successfully decoded, determining whether to give up the decoding operation of the first chunk according to a symptom weight of the first chunk and at least one symptom weight of at least one corresponding chunk.

    Flash memory controller
    103.
    发明授权
    Flash memory controller 有权

    公开(公告)号：US12236115B2

    公开(公告)日：2025-02-25

    申请号：US18412635

    申请日：2024-01-15

    Applicant: Silicon Motion, Inc.

    Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

    IPC: G11C7/00 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56

    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

    Flash memory apparatus and storage management method for flash memory
    104.
    发明授权
    Flash memory apparatus and storage management method for flash memory 有权

    公开(公告)号：US12197285B2

    公开(公告)日：2025-01-14

    申请号：US18498069

    申请日：2023-10-31

    Applicant: Silicon Motion, Inc.

    Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu ,  Jian-Dong Du

    IPC: G11C29/00 ,  G06F11/10 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C16/04

    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

    Method, memory controller, and memory system for reading data stored in flash memory
    105.
    发明授权
    Method, memory controller, and memory system for reading data stored in flash memory 有权

    公开(公告)号：US12164377B2

    公开(公告)日：2024-12-10

    申请号：US18379154

    申请日：2023-10-11

    Applicant: Silicon Motion, Inc.

    Inventor： Tsung-Chieh Yang

    IPC: G06F11/00 ,  G06F11/10 ,  G11C11/56 ,  G11C16/26 ,  G11C29/02 ,  G11C29/52 ,  H03M13/11 ,  G11C29/04

    Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

    CONTROL METHOD OF MEMORY DEVICE AND ASSOCIATED FLASH MEMORY CONTROLLER
    106.
    发明公开
    CONTROL METHOD OF MEMORY DEVICE AND ASSOCIATED FLASH MEMORY CONTROLLER 审中-公开

    公开(公告)号：US20240329871A1

    公开(公告)日：2024-10-03

    申请号：US18128244

    申请日：2023-03-30

    Applicant: Silicon Motion, Inc.

    Inventor： Tsung-Chieh Yang

    IPC: G06F3/06

    CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679

    Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the flash memory module includes a plurality of blocks. The control method includes the steps of: obtaining a read count of a specific block; obtaining a time stamp of the specific block, wherein the time stamp is a write time of the specific block; calculating a time difference between a current system time and the time stamp of the specific block; and using the read count of the specific block and the time difference, and referring to a read count and threshold time mapping table to determine whether to arrange the specific block in a garbage collection pool.

    Method and apparatus for performing data management of memory device with aid of targeted protection control
    107.
    发明授权
    Method and apparatus for performing data management of memory device with aid of targeted protection control 有权

    公开(公告)号：US12014087B2

    公开(公告)日：2024-06-18

    申请号：US17869735

    申请日：2022-07-20

    Applicant: Silicon Motion, Inc.

    Inventor： Tsung-Chieh Yang

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A method for performing data management of a memory device with aid of targeted protection control and associated apparatus are provided. The method may include: receiving a first host command from a host device; sending a first operating command to a non-volatile (NV) memory to read first stored data from a first location within the NV memory; monitoring a read count of the first location to determine whether the read count of the first location reaches a read count threshold; monitoring at least one error bit count of other stored data of at least one other location within the NV memory to determine whether the at least one error bit count reaches an error bit count threshold; and starting a targeted protection procedure to process second stored data, for preventing the second stored data from being damaged by at least one reading behavior of the host device.

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