公开(公告)号：US06400180B2

公开(公告)日：2002-06-04

申请号：US09861261

申请日：2001-05-18

申请人： Ralph D. Wittig ,  Sundararajarao Mohan ,  Bernard J. New

发明人： Ralph D. Wittig ,  Sundararajarao Mohan ,  Bernard J. New

IPC分类号： H01L2500

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17728

摘要： A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

摘要翻译： 用于现场可编程门阵列（FPGA）的可配置逻辑元件（CLE）包括“扩展器”，即允许逻辑块之间的快速信号通信的连接器。 扩展器允许多个逻辑块或其部分的可配置互连形成可以实现诸如PAL，查找表，多路复用器，三态缓冲器和存储器之类的大型用户电路的单个逻辑实体。 一个实施例包括可配置逻辑块。 在第一模式中，逻辑块提供具有N个共享输入和两个单独输出的两个N输入LUT。 然后使用扩展器组合输出以产生（N + 1） - 输入功能。 在第二模式中，逻辑块提供具有M个非共享输入的两个N输入LUT。 可选的第三模式基于N个输入信号的值提供多个产品项输出信号。

公开(公告)号：US06388466B1

公开(公告)日：2002-05-14

申请号：US09844042

申请日：2001-04-27

申请人： Ralph D. Wittig ,  Sundararajarao Mohan ,  Bernard J. New

发明人： Ralph D. Wittig ,  Sundararajarao Mohan ,  Bernard J. New

IPC分类号： H03K19177

CPC分类号： H03K19/17728 ,  H03K19/1736 ,  H03K19/1737

摘要： A logic element for a programmable logic device (PLD) can be configured as a shift register of variable length. An array of memory cells in the logic element is divided into two or more portions. The memory cells of each portion supply values to a corresponding output multiplexing circuit, thereby enabling the logic element to function as a lookup table by combining the outputs of the multiplexing circuits. However, each portion is also configurable as a shift register. The portions can function as separate shift registers, or can be concatenated to function as a single shift register. In some embodiments, the portions can also be concatenated with shift registers in other logic elements. Because two or more output multiplexing circuits are available, two or more taps are provided, one from each portion of the memory array.

摘要翻译： 可编程逻辑器件（PLD）的逻辑元件可以被配置为可变长度的移位寄存器。 逻辑元件中的一组存储单元被分成两部分或更多部分。 每个部分的存储单元将值提供给相应的输出多路复用电路，从而使逻辑元件能够通过组合多路复用电路的输出作为查找表。 然而，每个部分也可配置为移位寄存器。 这些部分可以用作单独的移位寄存器，或者可以连接起来作为单个移位寄存器。 在一些实施例中，这些部分也可以与其它逻辑元件中的移位寄存器连接。 由于两个或多个输出多路复用电路可用，所以提供两个或更多个抽头，一个来自存储器阵列的每个部分。

公开(公告)号：US6154052A

公开(公告)日：2000-11-28

申请号：US244441

申请日：1999-02-04

申请人： Bernard J. New

发明人： Bernard J. New

IPC分类号： G06F7/50 ,  G06F7/503 ,  H03K19/173 ,  H03K19/177

CPC分类号： G06F7/503 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/1778

摘要： In an FPGA having a tristate bus structure formed by a multiplexer chain extending across a plurality of logic units, a programmable function generator is provided to interface between the input and enable signal lines of logic units and the corresponding multiplexer's input and control terminals and is coupled to receive a mode control signal. When the mode control signal is in a first logic state, the function generator couples the input and enable signals to the corresponding multiplexer input and control terminals to emulate a tristate input bus. When the mode control signal is in a second logic state, the function generator receives first and second data signals from corresponding input and enable lines. In response thereto, the function generator couples one of the data signals to the corresponding multiplexer input terminal and provides an exclusive-OR logic function of the first and second data signals to the corresponding multiplexer control terminal. In this manner, each multiplexer stage provides a carry signal to the next multiplexer stage, thereby forming a carry path in the horizontal direction across the FPGA.

摘要翻译： 在具有由跨越多个逻辑单元延伸的复用器链形成的三态总线结构的FPGA中，提供可编程函数发生器以在逻辑单元的输入和使能信号线与相应的多路复用器的输入和控制端之间进行接口， 以接收模式控制信号。 当模式控制信号处于第一逻辑状态时，功能发生器将输入和使能信号耦合到相应的多路复用器输入和控制端以仿真三态输入总线。 当模式控制信号处于第二逻辑状态时，函数发生器从相应的输入和使能线接收第一和第二数据信号。 响应于此，函数发生器将数据信号之一耦合到对应的多路复用器输入端，并将第一和第二数据信号的异或逻辑功能提供给对应的多路复用器控制端。 以这种方式，每个多路复用器级向下一个多路复用器级提供进位信号，由此在跨越FPGA的水平方向上形成一个进位路径。

公开(公告)号：US6046603A

公开(公告)日：2000-04-04

申请号：US989980

申请日：1997-12-12

申请人： Bernard J. New

发明人： Bernard J. New

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/17776 ,  H03K19/17752 ,  H03K19/17756

摘要： A field programmable gate array (FPGA) having an array of configurable logic blocks (CLBs) which can be partially reconfigured. Each column of CLBs is connected to a corresponding column select line, and each row of CLBs is connected to a corresponding row select line. A rectangular set of CLBs to be reconfigured is selected, wherein the rectangular set of CLBs is defined by the intersection of one or more consecutive columns of CLBs and one or more consecutive rows of CLBs. Column select signals are asserted on the column select lines associated with the one or more consecutive columns of CLBs. Similarly, row select signals are asserted on the row select lines associated with the one or more consecutive rows of CLBs. CLBs which receive both an asserted column select signal and an asserted row select signal are enabled for reconfiguration.

摘要翻译： 具有可部分重新配置的可配置逻辑块（CLB）阵列的现场可编程门阵列（FPGA）。 CLB的每列连接到相应的列选择线，并且CLB的每一行都连接到相应的行选择行。 选择要重新配置的一组CLB，其中CLB的矩形集由CLB的一个或多个连续列和CLB的一个或多个连续行的交集来定义。 在与CLB的一个或多个连续列相关联的列选择行上断言列选择信号。 类似地，在与CLB的一个或多个连续行相关联的行选择线上断言行选择信号。 接收断言的列选择信号和断言的行选择信号的CLB被启用以进行重新配置。

公开(公告)号：US5999025A

公开(公告)日：1999-12-07

申请号：US049853

申请日：1998-03-27

申请人： Bernard J. New

发明人： Bernard J. New

IPC分类号： G06F1/10 ,  H03L7/08 ,  H03L7/06

CPC分类号： G06F1/10 ,  H03L7/0807

摘要： A programmable logic device (PLD) which includes a phase comparator in addition to the conventional configurable logic circuitry normally present in the PLD. The configurable logic circuitry of the PLD includes a clock distribution circuit which is configured to route a clock signal VCO.sub.OUT generated by a voltage controlled oscillator (VCO) throughout the PLD as a distributed clock signal (DIST.sub.-- CLK). The DIST.sub.-- CLK signal is used to clock the output registers which route data values out of the PLD. The DIST.sub.-- CLK signal is also provided to the phase comparator. The phase comparator is also coupled to receive a clock signal CLK.sub.IN from an external device. In response, the phase comparator generates an error signal which is representative of the phase difference between the CLK.sub.IN and DIST.sub.-- CLK signals. This error signal is provided to a loop filter. In response, the loop filter generates a control signal, which in turn, controls the frequency of the VCO.sub.OUT signal generated by the VCO. The frequency of the VCO.sub.OUT signal is controlled such that the DIST.sub.-- CLK signal is synchronized with the CLK.sub.IN signal.

摘要翻译： 一种可编程逻辑器件（PLD），其包括通常存在于PLD中的常规可配置逻辑电路的相位比较器。 PLD的可配置逻辑电路包括时钟分配电路，其配置为将由压控振荡器（VCO）产生的时钟信号VCOOUT作为分布式时钟信号（DIST-CLK）传送到整个PLD。 DIST-CLK信号用于对从PLD中传出数据值的输出寄存器进行时钟。 DIST-CLK信号也提供给相位比较器。 相位比较器也被耦合以从外部设备接收时钟信号CLKIN。 作为响应，相位比较器产生代表CLKIN和DIST-CLK信号之间的相位差的误差信号。 该错误信号提供给环路滤波器。 作为响应，环路滤波器产生控制信号，控制信号又控制由VCO产生的VCOOUT信号的频率。 控制VCOOUT信号的频率使得DIST-CLK信号与CLKIN信号同步。

公开(公告)号：US5818255A

公开(公告)日：1998-10-06

申请号：US536287

申请日：1995-09-29

申请人： Bernard J. New ,  Danesh Tavana

发明人： Bernard J. New ,  Danesh Tavana

IPC分类号： H03K19/173 ,  H03K7/38 ,  H03K19/21

CPC分类号： H03K19/1737

摘要： A carry logic circuit for a programmable logic device which uses a single function generator to create a carry propagate signal (P) and an output signal (S). The function generator includes a plurality of signal generation circuits, each of which is controlled by a first input signal (A) and a second input signal (B). One of the signal generation circuits is programmed to provide a desired carry propagate signal (P) in response to the first and second input signals (A,B). The carry propagate signal (P) is transmitted for use outside of the function generator to perform a carry propagation function for the carry logic circuit. The remaining signal generation circuits are programmed to generate one or more intermediate output signals in response to the first and second input signals (A,B). These intermediate output signals, in combination with carry propagate signal (P), are representative of the desired output signal (S). The function generator also includes a signal selection circuit which is coupled to the signal generation circuits. The signal selection circuit passes a signal which is selected from the group consisting of the carry propagate signal (P) and the intermediate output signals, thereby providing the output signal (S).

摘要翻译： 一种用于可编程逻辑器件的进位逻辑电路，其使用单个函数发生器来产生进位传播信号（P）和输出信号（S）。 功能发生器包括多个信号产生电路，每个信号产生电路由第一输入信号（A）和第二输入信号（B）控制。 信号发生电路之一被编程为响应于第一和第二输入信号（A，B）提供期望的进位传播信号（P）。 发送进位传播信号（P）以在功能发生器外部使用，以对进位逻辑电路执行进位传播功能。 剩余的信号发生电路被编程为响应于第一和第二输入信号（A，B）产生一个或多个中间输出信号。 这些中间输出信号与进位传播信号（P）相结合，代表期望的输出信号（S）。 功能发生器还包括耦合到信号发生电路的信号选择电路。 信号选择电路通过从由进位传播信号（P）和中间输出信号组成的组中选择的信号，从而提供输出信号（S）。

公开(公告)号：US5450022A

公开(公告)日：1995-09-12

申请号：US319756

申请日：1994-10-07

申请人： Bernard J. New

发明人： Bernard J. New

IPC分类号： H03K3/037 ,  H03K17/687 ,  H03K17/693 ,  H03K3/356

CPC分类号： H03K17/6872 ,  H03K17/693 ,  H03K3/037

摘要： A structure and method for configuring a field programmable gate array (FPGA). A configuration memory cell within the FPGA receives a programming signal. In response, the configuration memory cell provides a signal to a configuration control circuit to configure the FPGA. The configuration memory cell includes an input lead, a storage device and a selectable configuration circuit. The input lead carries the programming signal to the storage device. The storage device stores the programming signal and an inverted programming signal which is the inverse of the programming signal. The selectable configuration circuit can be selectably configured to provide the programming signal or the inverted programming signal to a first input lead of the configuration control circuit. The configuration control circuit couples (or decouples) various elements of the FPGA in response to the signal provided on the first input lead.In an alternate embodiment, the selectable configuration circuit is coupled between the input lead and the storage device. Again, the selectable configuration circuit can be selectably configured to provide the programming signal or the inverted programming signal to the first input lead of the configuration control circuit.

摘要翻译： 用于配置现场可编程门阵列（FPGA）的结构和方法。 FPGA内的配置存储单元接收编程信号。 作为响应，配置存储单元向配置控制电路提供信号以配置FPGA。 配置存储单元包括输入引线，存储器件和可选配置电路。 输入引线将编程信号传送到存储设备。 存储装置存储编程信号和与编程信号相反的反相编程信号。 可选择配置电路可以可选地配置为将编程信号或反相编程信号提供给配置控制电路的第一输入引线。 配置控制电路响应于在第一输入引线上提供的信号来耦合（或解耦）FPGA的各种元件。 在替代实施例中，可选配置电路耦合在输入引线和存储器件之间。 再次，可选配置电路可以可选地配置成将编程信号或反相编程信号提供给配置控制电路的第一输入引线。

公开(公告)号：US4943940A

公开(公告)日：1990-07-24

申请号：US655482

申请日：1984-09-27

申请人： Bernard J. New

发明人： Bernard J. New

IPC分类号： G06F7/38 ,  G06F7/00 ,  G06F7/485 ,  G06F7/487 ,  G06F7/493 ,  G06F7/53 ,  G06F7/57 ,  G06F7/76

CPC分类号： G06F7/483 ,  G06F7/49905 ,  G06F7/49936 ,  G06F7/49947

摘要： A fully combinatorial floating point arithmetic apparatus is provided comprising separate fully combinatorial add/subtract and multiply assemblies which share a common normalization, rounding and exponential processing apparatus.

摘要翻译： 提供了一种完全组合的浮点运算装置，其包括共享共同的归一化，舍入和指数处理装置的分离的完全组合的加/减和乘法组件。

公开(公告)号：US4748582A

公开(公告)日：1988-05-31

申请号：US747073

申请日：1985-06-19

申请人： Bernard J. New ,  Timothy J. Flaherty

发明人： Bernard J. New ,  Timothy J. Flaherty

IPC分类号： G06F7/53 ,  G06F7/508 ,  G06F7/52 ,  G06F7/533

CPC分类号： G06F7/5312 ,  G06F7/49994

摘要： A compact rectangular parallel multiplier array of Booth summation cells includes along a left edge a cell which reduces to two the number of sign-extension bits sufficient to generate subsequent intermediate products. The cell employs optimized logic circuitry which generates a sum, a carry and a guard bit for use during generation of the next most-significant intermediate product.

摘要翻译： 布斯求和单元的紧凑的矩形平行乘法器阵列包括沿着左边缘的单元，其将足以产生后续中间乘积的符号扩展位的数量减少到两个。 该小区采用优化的逻辑电路，其产生在下一个最重要的中间产品的生成期间使用的总和，进位和保护位。

公开(公告)号：US4621341A

公开(公告)日：1986-11-04

申请号：US644403

申请日：1984-08-24

申请人： Bernard J. New

发明人： Bernard J. New

IPC分类号： G06F7/00 ,  G06F12/00 ,  G06F12/04 ,  G06F13/40 ,  G06F3/00

CPC分类号： G06F13/4018

摘要： A method and apparatus for transferring data in parallel from a smaller to a larger register is described, in which the larger register comprises a first and a second set of master and slave latches with a one shot employed for clocking the master latches in the first set. In operation, a first word from the smaller register is latched into the first set of master latches in response to an output from the one shot which occurs on the trailing edge of a clock pulse applied to the larger register. On the leading edge of a subsequent clock pulse applied to the larger register, a second data word is latched in the second set of master latches. Immediately thereafter the first and the second set of slave latches are opened for transferring the first and second words at their inputs to their outputs in parallel. Following the transfer of the first and second words to the outputs of the first and second set of slave latches, the slave latches close, latching the first and second words. Immediately thereafter the first and second master latches open to begin the next cycle of data transfer.

摘要翻译： 描述了用于从较小寄存器到较大寄存器并行传送数据的方法和装置，其中较大的寄存器包括第一和第二组主锁存器和从锁存器，其具有用于对第一组中的主锁存器进行计时的一次 。 在操作中，响应于在施加到较大寄存器的时钟脉冲的后沿发生的一次触发的输出，来自较小寄存器的第一个字被锁存到第一组主锁存器中。 在施加到较大寄存器的后续时钟脉冲的前沿，第二个数据字被锁存在第二组主锁存器中。 此后立即打开第一组和第二组从属锁存器，用于将其输入端的第一个和第二个字并行传输到其输出端。 在将第一和第二个字传送到第一和第二组从锁存器的输出之后，从锁存器闭合，锁存第一和第二字。 此后，第一和第二主锁存器立即打开以开始下一个数据传输周期。