公开(公告)号：US11258154B2

公开(公告)日：2022-02-22

申请号：US16700476

申请日：2019-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adam Joseph Fruehling ,  Benjamin Stassen Cook ,  Juan Alejandro Herbsommer ,  Swaminathan Sankaran

IPC: H01P5/107 ,  H01P3/12 ,  H01P5/02 ,  H01P7/06 ,  G04F5/14 ,  H01P1/20 ,  H01Q15/00

Abstract: An apparatus includes a substrate containing a cavity and a dielectric structure covering at least a portion of the cavity. The cavity is hermetically sealed. The apparatus also may include a launch structure formed on the dielectric structure and outside the hermetically sealed cavity. The launch structure is configured to cause radio frequency (RF) energy flowing in a first direction to enter the hermetically sealed cavity through the dielectric structure in a direction orthogonal to the first direction.

公开(公告)号：US11133375B2

公开(公告)日：2021-09-28

申请号：US16905197

申请日：2020-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Roberto Giampiero Massolini ,  Daniel Carothers

IPC: H01L21/00 ,  H01L49/02 ,  H01L23/495 ,  H01L27/06 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00

Abstract: In an integrated circuit (IC), a semiconductor substrate has a first side and an opposite second side. The second side has a trench. Circuitry is on the first side. An inductive structure is within the trench. The inductive structure is connected to the circuitry through vias in the semiconductor substrate. The semiconductor substrate is mounted on a package substrate. At least a portion of the inductive structure contacts the package substrate. The circuitry is coupled to the inductive structure through wires to the package substrate.

公开(公告)号：US11128023B2

公开(公告)日：2021-09-21

申请号：US16716642

申请日：2019-12-17

Applicant: Texas Instruments Incorporated

Inventor： Hassan Omar Ali ,  Juan Alejandro Herbsommer ,  Benjamin Stassen Cook ,  Vikas Gupta ,  Athena Lin ,  Swaminathan Sankaran

IPC: H01P3/16 ,  H01Q1/22 ,  H04B1/40 ,  H01P3/12

Abstract: A device includes a multilayer substrate having a first surface and a second surface opposite the first surface. An integrated circuit is mounted on the second surface of the multilayer substrate, the integrated circuit having transmission circuitry configured to process millimeter wave signals. A substrate waveguide having a substantially solid wall is formed within a portion of the multilayer substrate perpendicular to the first surface. The substrate waveguide has a first end with the wall having an edge exposed on the first surface of the multilayer substrate. A reflector is located in one of the layers of the substrate and is coupled to an edge of the wall on an opposite end of the substrate waveguide.

公开(公告)号：US20210272804A1

公开(公告)日：2021-09-02

申请号：US17315524

申请日：2021-05-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/373 ,  H01L21/56 ,  H01L23/433 ,  H01L23/367

Abstract: A packaged electronic device includes an integrated circuit and an electrically non-conductive encapsulation material in contact with the integrated circuit. A thermal conduit extends from an exterior of the package, through the encapsulation material, to the integrated circuit. The thermal conduit has a thermal conductivity higher than the encapsulation material contacting the thermal conduit. The thermal conduit includes a cohered nanoparticle film. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US11063120B2

公开(公告)日：2021-07-13

申请号：US16232123

申请日：2018-12-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Luigi Colombo ,  Archana Venugopal ,  Benjamin Stassen Cook ,  Nazila Dadvand

IPC: H01L29/16 ,  H01L21/768 ,  C01B32/194 ,  H01L23/532 ,  H01L27/06 ,  H01L29/06 ,  C23C16/26 ,  H01L21/02 ,  C01B32/184 ,  C25D11/00 ,  C23C16/02 ,  B05D1/00 ,  H01L23/00

Abstract: A structure includes a metal layer and a plurality of interconnected unit cells forming a lattice contained at least partly within the metal layer, including at least a first unit cell formed of first interconnected graphene tubes, and a second unit cell formed of second interconnected graphene tubes, wherein the metal layer protrudes through holes within the lattice.

公开(公告)号：US20210090904A1

公开(公告)日：2021-03-25

申请号：US17114240

申请日：2020-12-07

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Daniel Lee Revier

IPC: H01L21/56 ,  H01L23/31

Abstract: In described examples, a method for encapsulating a semiconductor device includes the steps of immersing a layer of the semiconductor device in a liquid encapsulation material, irradiating portions of the liquid encapsulation material to polymerize the liquid encapsulation material, and moving the semiconductor device further from a surface of the liquid encapsulation material proximate to the layer. Immersing the semiconductor device is performed to cover a layer of the device in the liquid encapsulation material. Targeted locations of the liquid encapsulation material covering the layer are irradiated to form solid encapsulation material. The semiconductor device is moved from a surface of the liquid encapsulation material so that a new layer of the semiconductor device and/or of the solid encapsulation material can be covered by the liquid encapsulation material. The irradiating and moving steps are then repeated until a three dimensional structure on the semiconductor device is formed using the solid encapsulation material.

公开(公告)号：US20200381517A1

公开(公告)日：2020-12-03

申请号：US16995563

申请日：2020-08-17

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Luigi Colombo ,  Nazila Dadvand ,  Archana Venugopal

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/808 ,  H01L29/423

Abstract: A switchable array includes: a microstructure of interconnected units formed of graphene tubes with open spaces in the microstructure bounded by the graphene tubes; at least one JFET gate in at least one of the graphene tubes; and a control line having an end connected to the at least one JFET gate. The control line extends to a periphery of the microstructure.

公开(公告)号：US20200312747A1

公开(公告)日：2020-10-01

申请号：US16363468

申请日：2019-03-25

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

公开(公告)号：US10790228B2

公开(公告)日：2020-09-29

申请号：US16372455

申请日：2019-04-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L21/288 ,  H01L23/367 ,  H01L23/373 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/285 ,  H01L21/3205 ,  H01L23/48

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

公开(公告)号：US10775422B2

公开(公告)日：2020-09-15

申请号：US15695651

申请日：2017-09-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adam Joseph Fruehling ,  Juan Alejandro Herbsommer ,  Benjamin Stassen Cook ,  Swaminathan Sankaran

IPC: G01N22/00 ,  G01R23/16 ,  H03L7/26 ,  H01P7/06

Abstract: A device includes a substrate that includes a resonant cavity. The resonant cavity includes a plurality of dipolar molecules that have an absorption frequency. The resonant cavity resonates at a frequency that is equal to the absorption frequency of the dipolar molecules. The device further includes a first port on the resonant cavity configured to receive a radio frequency (RF) signal.