公开(公告)号：US11532713B2

公开(公告)日：2022-12-20

申请号：US17091159

申请日：2020-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

公开(公告)号：US11502201B2

公开(公告)日：2022-11-15

申请号：US17081915

申请日：2020-10-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Shih-Chuan Chiu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, a dielectric layer in contact with the second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature, and the second surface of the semiconductor layer is co-planar with the second surface of the source/drain feature, and a gate structure having a surface in contact with the first surface of the semiconductor layer.

公开(公告)号：US11476196B2

公开(公告)日：2022-10-18

申请号：US16597205

申请日：2019-10-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/532 ,  H01L29/78 ,  H01L21/768 ,  H01L29/40 ,  H01L23/522 ,  H01L29/417

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.

公开(公告)号：US11456209B2

公开(公告)日：2022-09-27

申请号：US17092773

申请日：2020-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

公开(公告)号：US20220246740A1

公开(公告)日：2022-08-04

申请号：US17728679

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/08 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

Abstract: A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact.

公开(公告)号：US11257926B2

公开(公告)日：2022-02-22

申请号：US16895604

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

公开(公告)号：US11251305B2

公开(公告)日：2022-02-15

申请号：US16808770

申请日：2020-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/28

Abstract: A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes a cap layer formed over the gate structure. The structure also includes a contact structure formed over the gate structure penetrating through the cap layer. The structure also includes an isolation film formed over sidewalls of the contact structure. The isolation film is separated from the gate structure, and a bottom surface of the isolation film is below a top surface of the cap layer.

公开(公告)号：US11239106B2

公开(公告)日：2022-02-01

申请号：US16947932

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/762 ,  H01L21/311 ,  H01L27/088

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

公开(公告)号：US11195934B2

公开(公告)日：2021-12-07

申请号：US16895534

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213

Abstract: The present disclosure provides embodiments of a semiconductor structure having bi-layer self-aligned contact. The semiconductor structure includes a gate stack disposed on a semiconductor substrate and having a first height, a spacer disposed on a sidewall of the gate stack and having a second height greater than the first height, and a first etch stop layer disposed on a sidewall of the gate spacer and having a third height greater than the second height. The semiconductor structure further includes a first dielectric layer disposed over the gate stack and contacting the gate spacer and the first etch stop layer and a second dielectric layer disposed on the first dielectric layer and contacting the first etch stop layer.

公开(公告)号：US20210376111A1

公开(公告)日：2021-12-02

申请号：US16888138

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hai-Ching Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: A method includes providing a structure having a gate stack; first gate spacers; a second gate spacer over one of the first gate spacers and having an upper portion over a lower portion; a dummy spacer; an etch stop layer; and a dummy cap. The method further includes removing the dummy cap, resulting in a first void above the gate stack and between the first gate spacers; removing the dummy spacer, resulting in a second void above the lower portion and between the etch stop layer and the upper portion; depositing a layer of a decomposable material into the first and the second voids; depositing a seal layer over the etch stop layer, the first and the second gate spacers, and the layer of the decomposable material; and removing the layer of the decomposable material, thereby reclaiming at least portions of the first and the second voids.