公开(公告)号：US11257807B2

公开(公告)日：2022-02-22

申请号：US17111220

申请日：2020-12-03

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.

公开(公告)号：US10546849B2

公开(公告)日：2020-01-28

申请号：US15247134

申请日：2016-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Hou-Jen Chiu ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

Abstract: A semiconductor structure for electrostatic discharge (ESD) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. The first doped well is disposed in the substrate and has a first conductive type. The source doped region is disposed in the substrate and has a second conductive type opposite to the first conductive type. The drain doped region is disposed in the substrate and has the second conductive type. The gate structure is disposed on the substrate and between the source doped region and the drain doped region. The gate structure is separated from the source doped region.

公开(公告)号：US20190229531A1

公开(公告)日：2019-07-25

申请号：US15878421

申请日：2018-01-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Liao ,  Ting-Yao Lin ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H02H9/04 ,  H02H1/00 ,  H01L27/02

Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.

公开(公告)号：US10262987B2

公开(公告)日：2019-04-16

申请号：US15481444

申请日：2017-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H01L27/02 ,  H02H9/04

Abstract: The present invention provides an ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit includes a bipolar junction transistor (BJT) and a trigger source. A collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line. The trigger source is electrically connected between the base of the BJT and the high voltage power line.

公开(公告)号：US20180358294A1

公开(公告)日：2018-12-13

申请号：US15667637

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L23/5223

Abstract: An electric connector includes a metal interconnect, a first vertical element and a second vertical element. The metal interconnect includes a plurality of horizontal elements. The first vertical element physically connects to a top surface of each of the horizontal elements. The second vertical element physically connects to a bottom surface of each of the horizontal elements, and the second vertical element misaligns the first vertical element. The present invention also provides an electric connector including a first vertical element and a second vertical element. The first vertical element physically connects to a top surface of a horizontal element. The second vertical element physically connects to a bottom surface of the horizontal element, and the second vertical element misaligns the first vertical element, wherein the first vertical element or the horizontal element is burned out before the second vertical element is burned out while a voltage is applied.

公开(公告)号：US20180254268A1

公开(公告)日：2018-09-06

申请号：US15445999

申请日：2017-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Yen ,  Po-Ya Lai ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/749 ,  H01L29/66

CPC classification number: H01L27/027 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/66356 ,  H01L29/749

Abstract: An ESD protection device includes a semiconductor substrate, a well, a gate structure, a first source/drain region, a second source/drain region, a first doped region, and a second doped region. The well is disposed in the semiconductor substrate. The gate structure is disposed on the well. The first source/drain region and the second source/drain region are disposed in the well and disposed at two opposite sides of the gate structure respectively. The first doped region is disposed in the first source/drain region. The second doped region is disposed in the second source/drain region. A conductivity type of the first doped region is complementary to that of the first source/drain region. A conductivity type of the second doped region is complementary to that of the second source/drain region. A conductivity type of the well is complementary to that of the first source/drain region and the second source/drain region.

公开(公告)号：US10068896B1

公开(公告)日：2018-09-04

申请号：US15445999

申请日：2017-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Yen ,  Po-Ya Lai ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/06 ,  H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/749 ,  H01L29/66

Abstract: An ESD protection device includes a semiconductor substrate, a well, a gate structure, a first source/drain region, a second source/drain region, a first doped region, and a second doped region. The well is disposed in the semiconductor substrate. The gate structure is disposed on the well. The first source/drain region and the second source/drain region are disposed in the well and disposed at two opposite sides of the gate structure respectively. The first doped region is disposed in the first source/drain region. The second doped region is disposed in the second source/drain region. A conductivity type of the first doped region is complementary to that of the first source/drain region. A conductivity type of the second doped region is complementary to that of the second source/drain region. A conductivity type of the well is complementary to that of the first source/drain region and the second source/drain region.

公开(公告)号：US10062751B2

公开(公告)日：2018-08-28

申请号：US15402204

申请日：2017-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hou-Jen Chiu ,  Ya-Ting Lin ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L29/0653 ,  H01L29/785

Abstract: A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. The shallow trench isolation is disposed in the substrate and surrounds the fin shaped structure. The diffusion break structure is disposed in the fin shaped structure, and the gate electrode is disposed across the fin shaped structure.

公开(公告)号：US20180114787A1

公开(公告)日：2018-04-26

申请号：US15365602

申请日：2016-11-30

Applicant: United Microelectronics Corp.

Inventor： Heng-Yu Lin ,  Kuei-Chih Fan ,  Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L27/0274 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/7816 ,  H01L29/7835

Abstract: An ESD protection device on a substrate includes a base doped region of a first conductivity type. A first inter doped region of a second conductivity type is in the base doped region. A drain region of the second conductivity type in the first inter doped region is connected to a first electrode terminal. An inserted doped region of the first conductivity type is in the drain region. A second inter doped region of the second conductivity type is in the base doped region. A source region of the second conductivity type is in the second inter doped region. A substrate-surface doped region of the first conductivity type in the substrate is adjacent to or in contact with the source region. A gate structure is between the drain and source regions in the substrate. The substrate-surface doped region and the source region are connected to a second electrode terminal.

公开(公告)号：US09825021B2

公开(公告)日：2017-11-21

申请号：US14685588

申请日：2015-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/02 ,  H01L23/60 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L23/60 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.