公开(公告)号：US06204795B1

公开(公告)日：2001-03-20

申请号：US09227994

申请日：1999-01-08

Applicant: Morteza Afghahi

Inventor： Morteza Afghahi

IPC: H03M150

CPC classification number: H03M1/48 ,  H04N5/376

Abstract: A method is provided having the steps of receiving a first pixel signal; generating a first set of bits representative of the first pixel signal; receiving a second pixel signal; and, generating a second set of bits representative of a difference between the first pixel signal and the second pixel signal. An apparatus and system for performing the above method is also provided.

Abstract translation: 提供一种具有接收第一像素信号的步骤的方法; 产生表示第一像素信号的第一组位; 接收第二像素信号; 以及产生代表第一像素信号和第二像素信号之间的差的第二组位。 还提供了用于执行上述方法的装置和系统。

公开(公告)号：US5297106A

公开(公告)日：1994-03-22

申请号：US769302

申请日：1991-10-01

Applicant: Paul E. Green

Inventor： Paul E. Green

IPC: H04N5/353 ,  H04N5/357 ,  H04N5/376 ,  H04N3/14

CPC classification number: H04N5/3572 ,  H04N5/376

Abstract: A METHOD AND APPARATUS FOR CONTROLLING INTEGRATION TIME ON MULTIPLEXING STARING ARRAYS for selecting all or any portion of each row integration scan for charging integration capacitors from a scanned staring array by providing a row ON selection clock signal, providing a signal corresponding to all or a portion of the time the row is to be connected to the capacitors, and nanding the row ON signal and the corresponding signal to select the time allotted for charging said capacitors.

Abstract translation: 一种用于控制多重启动阵列的集成时间的方法和装置，用于通过提供行ON选择时钟信号，从扫描的起始阵列中选择用于对积分电容器进行充电积分电容的全部或任何部分，提供对应于全部或部分的信号 将该行连接到电容器的时间，以及对该行ON信号和相应的信号进行定位以选择分配用于对所述电容器充电的时间。

公开(公告)号：US11665448B2

公开(公告)日：2023-05-30

申请号：US17386356

申请日：2021-07-27

Applicant: Sony Semiconductor Solutions Corporation

Inventor： Yusuke Minagawa ,  Toru Akishita

IPC: H04N5/376 ,  H04N5/347 ,  H04N5/3745

CPC classification number: H04N5/376 ,  H04N5/347 ,  H04N5/3745

Abstract: An information processing apparatus including a specification section specifying, from among a plurality of blocks that are set by dividing pixels included in at least a partial region of a pixel region having a plurality of pixels arrayed therein and each of which includes at least one or more of the pixels, at least one or more of the blocks, and a generation section generating a unique value based on pixel values of the pixels included in the specified blocks.

公开(公告)号：US20190052829A1

公开(公告)日：2019-02-14

申请号：US15675803

申请日：2017-08-14

Applicant: Himax Imaging Limited

Inventor： Yuan-Chih Peng ,  Ching-Fong Chen

IPC: H04N5/376 ,  G06T3/40 ,  H04N5/262

CPC classification number: H04N5/3765 ,  G06T3/4053 ,  H04N5/23296 ,  H04N5/2628 ,  H04N5/3454 ,  H04N5/361 ,  H04N5/374 ,  H04N5/376

Abstract: An image pickup apparatus includes an image sensor array, a scaling circuit, an output circuit and a timing control circuit. The image sensor array reads N pixel lines according to a read timing control signal to capture N lines of pixel data of a source image. The scaling circuit receives the N lines of pixel data according to a scaling timing control signal, and refers to a scaling factor to scale up the source image to generate an upscaled image having M lines of pixel data. M is a positive integer greater than N. The output circuit outputs the M lines of pixel data according to an output timing. The timing control circuit determines a receiving timing according to the output timing and the scaling factor to generate the scaling timing control signal, and determines a read timing according to the receiving timing to generate the read timing control signal.

公开(公告)号：US20180352178A1

公开(公告)日：2018-12-06

申请号：US15761721

申请日：2016-08-31

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： AKIHIKO KATO ,  HUNG LUONG

IPC: H04N5/357 ,  H04N5/374 ,  H04N5/376 ,  H04N5/378 ,  H04N5/353

CPC classification number: H04N5/357 ,  H04N5/374 ,  H04N5/376 ,  H04N5/378

Abstract: A solid-state image pickup element according to the present disclosure includes: an analog circuit unit configured to perform reading of a pixel signal from a unit pixel and to perform A/D conversion processing; a digital circuit unit configured to perform signal output processing of outputting pixel data after the A/D conversion processing, in parallel with the reading of the pixel signal and the A/D conversion processing; and a control unit configured to cause the digital circuit unit to perform the processing over a period from a processing start timing to a processing finish timing in the analog circuit unit, while the control unit is controlling a speed of a clock being a criterion for an operation of the digital circuit unit.

公开(公告)号：US20180262665A1

公开(公告)日：2018-09-13

申请号：US15896807

申请日：2018-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Jae Jung ,  Jun Seok Kim ,  Hyun Surk Ryu ,  Yun Jae Suh ,  Bong Ki Son ,  Seol Namgung ,  Keun Joo Park

IPC: H04N5/235 ,  G06T7/20 ,  G06F3/06 ,  H01L27/146

CPC classification number: H04N5/2351 ,  G06F3/0656 ,  G06T7/20 ,  G09G3/20 ,  G09G2310/0213 ,  G09G2360/142 ,  G09G2380/10 ,  H01L27/1463 ,  H04N5/351 ,  H04N5/3745 ,  H04N5/376

Abstract: An event detecting device may include an event signal generator configured to output a plurality of event signals, each including a first data and a second data having mutually complementary attributes and respective address data indicating positions of pixels having output the first data and the second data, a data manager configured to store one of the first data and the second data of a first one of the plurality of event signals and the respective address data in a buffer as first sub data when only one of the first data and the second data of the first one of the plurality of event signals includes the event information, and an output signal generator configured to generate an output signal using the first sub data and a second sub data when the second sub data, different from the first sub data, is stored in the buffer.

公开(公告)号：US20180255260A1

公开(公告)日：2018-09-06

申请号：US15971460

申请日：2018-05-04

Applicant: SONY CORPORATION

Inventor： Tsutomu NAKAJIMA ,  Atsushi MUTO

IPC: H04N5/3745 ,  H04N5/376 ,  H01L27/146

CPC classification number: H04N5/37455 ,  H01L27/14607 ,  H01L27/14634 ,  H01L27/14643 ,  H04N5/374 ,  H04N5/376 ,  H04N5/379

Abstract: The present technology relates to an image sensor and an electronic apparatus which can make the image sensor a smaller without degrading performance of the image sensor. The image sensor includes a pixel array unit in which pixels including photoelectric conversion elements are arranged in a two dimensional manner, a row circuit configured to control row scanning of the pixel array unit, and a column processing unit configured to convert an analog signal read out from the pixel array unit into a digital signal. The pixel array unit is disposed on a first-layer substrate, and the row circuit and the column processing unit are disposed on different substrates which are underlying layers of the first-layer substrate and which are laminated on the first-layer substrate. The present technology is applicable to the image sensor.

公开(公告)号：US10057514B2

公开(公告)日：2018-08-21

申请号：US15297685

申请日：2016-10-19

Applicant: OLYMPUS CORPORATION

Inventor： Masato Osawa

IPC: H04N5/335 ,  H04N5/341 ,  H04N5/378 ,  H04N5/369 ,  H04N5/3745 ,  H04N5/376

CPC classification number: H04N5/341 ,  H04N5/3692 ,  H04N5/3698 ,  H04N5/37457 ,  H04N5/376 ,  H04N5/3765 ,  H04N5/378

Abstract: An image sensor includes n light receiving elements including first to n-th light receiving elements, each of the light receiving elements generating photoelectric conversion signals, n sequencers including first to n-th sequencers, each of the sequencers having both a sequencer input terminal to which a k-th horizontal control signal is input, and a sequencer output terminal from which a (k+1)-th horizontal control signal is output, and n switches including first to n-th switches, each of the switches having a switch input terminal to which a signal corresponding to the photoelectric conversion signal is input, a switch control terminal to which a k-th pixel control signal is input, and a switch output terminal which is electrically connected to the switch input terminal, wherein n is a natural number of 2 or more, and k is a natural number of 1 to n.

公开(公告)号：US09974431B2

公开(公告)日：2018-05-22

申请号：US15090905

申请日：2016-04-05

Applicant: OLYMPUS CORPORATION

Inventor： Satoru Adachi

IPC: H04N9/64 ,  H04N3/14 ,  H04N5/335 ,  A61B1/05 ,  H04N5/361 ,  H04N5/376 ,  A61B1/00 ,  H04N5/225 ,  H04N5/357

CPC classification number: A61B1/051 ,  A61B1/00009 ,  H04N5/2256 ,  H04N5/357 ,  H04N5/361 ,  H04N5/376 ,  H04N5/3765 ,  H04N2005/2255

Abstract: An image sensor includes: a reference signal generation unit configured to generate and output a reference signal in accordance with a predetermined voltage; a plurality of pixels disposed in a two-dimensional matrix form and configured to receive light from outside, and to generate and output an imaging signal in accordance with an amount of the received light; a transfer unit configured to transfer the reference signal output from the reference signal generation unit and the imaging signal output from each of the plurality of pixels, during different periods; and an output unit configured to separately hold the reference signal and the imaging signal transferred from the transfer unit, sequentially switch between the reference signal and the imaging signal to output the switched signal.

公开(公告)号：US09961289B2

公开(公告)日：2018-05-01

申请号：US15028755

申请日：2014-10-10

Applicant: E2V SEMICONDUCTORS

Inventor： Bruno Diasparra

IPC: H04N5/335 ,  H04N3/14 ,  H04N5/376 ,  H04N5/353 ,  H04N5/378

CPC classification number: H04N5/3765 ,  H04N5/353 ,  H04N5/376 ,  H04N5/378

Abstract: The invention relates to image sensors and more specifically the generation of control signals for pixels and readout circuits.The sequencing circuit which produces these signals comprises: a programmable memory (MEM) containing binary words (M0, M1, M2, etc.) in which each word comprises a group of several bits of position 1 to N, and in which the position i of a bit in a word corresponds to the position i of a respective control signal; a memory controller (CTRL_MEM) for extracting from the memory at a determined rate the words located at successive addresses of the memory from a start address to an end address; and a control signal generation circuit (GEN_TIMING) establishing each control signal of position i from the succession of bits of respective position i that are extracted from the memory by the controller, the control signal reproducing the successive values taken by the bit of position i at the clock rate.