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公开(公告)号：US10742918B2
公开(公告)日：2020-08-11
申请号：US16126092
申请日：2018-09-10
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa
IPC: H04N5/3745 , H04N5/378 , H03M1/18 , H03M1/46 , H03M1/12
Abstract: An AD converter includes a first DAC circuit, a second DAC circuit, a comparison circuit, a control circuit, and a control switch. The comparison circuit is connected to a first output node of the first DAC circuit and a second output node of the second DAC circuit and compares an electric potential of the first output node with an electric potential of the second output node. The control circuit controls the first DAC circuit and the second DAC circuit in accordance with a result of the comparison acquired by the comparison circuit. The control switch controls turning on and off of connection between a first input node of the first DAC circuit and a second input node of the second DAC circuit.
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公开(公告)号：US10298216B2
公开(公告)日：2019-05-21
申请号：US15837299
申请日：2017-12-11
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada , Masato Osawa , Hideki Kato
Abstract: A semiconductor device is provided that includes an amplification circuit, a downstream circuit, and a clipping circuit. The amplification circuit includes a sampling capacitor, a feedback capacitor, and an operational amplifier circuit. The sampling capacitor holds air input signal on which sampling is performed, as a signal whose reference is a first reference voltage. The signal that is held in the sampling capacitor is transferred to the feedback capacitor. The operational amplifier circuit amplifies the signal that is held in the sampling capacitor, according to a ratio between values of the sampling capacitor and the feedback capacitor, and outputs the amplified signal, as a signal whose reference is a second reference voltage. The clipping circuit limits a voltage of an output signal of the operational amplifier circuit to a predetermined voltage or below.
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公开(公告)号：US20180367160A1
公开(公告)日：2018-12-20
申请号：US15998842
申请日：2018-08-17
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa , Yasunari Harada , Shuzo Hiraide , Hideki Kato
IPC: H03M1/46 , H04N5/378 , H04N9/04 , H04N5/3745
CPC classification number: H03M1/466 , H03M1/123 , H03M1/468 , H04N5/3742 , H04N5/37455 , H04N5/378 , H04N9/0455
Abstract: In an AD converter, a first DAC circuit performs a first operation in parallel with a second operation performed by a second DAC circuit, and the first DAC circuit performs the second operation in parallel with the first operation performed by the second DAC circuit. In the first operation, electric charge corresponding to an input signal of the first DAC circuit or an input signal of the second DAC circuit is sampled. In the second operation, an AD conversion is sequentially performed on the basis of the electric charge sampled in the first operation. The first DAC circuit and the second DAC circuit alternately perform the first operation and the second operation.
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公开(公告)号：US20140121552A1
公开(公告)日：2014-05-01
申请号：US13869586
申请日：2013-04-24
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa
CPC classification number: A61B5/046 , A61B5/0456 , A61B5/7225 , A61B5/7228 , A61N1/3925 , A61N1/3956
Abstract: To provide a fibrillation detector and a defibrillator that are capable of correctly detecting within a short time a ventricular fibrillation (VF) that shows an irregular amplitude or shape, an R-wave detection unit R_DETECT_MEAN converts power of a frequency component making up an R wave of an electrocardio signal ECG into an approximately DC component, and outputs the converted power as R-wave power V_R. A T-wave detection unit T_DETECT_MEAN converts power of a frequency component making up a T wave of the electrocardio signal ECG into an approximately DC component, and outputs the converted power as T-wave power V_T. The R-wave power V_R and the T-wave power V_T are input to a comparison unit CMP, and the comparison unit CMP outputs a magnitude comparison result between the R-wave power V_R and the T-wave power V_T as a comparison signal sig_comp.
Abstract translation: 为了提供能够在短时间内正确检测显示不规则振幅或形状的心室颤动（VF）的原纤颤检测器和除颤器，R波检测单元R_DETECT_MEAN转换构成R波的频率分量的功率 的心电信号ECG输入到大约DC分量中，并将转换的功率作为R波功率V_R输出。 T波检测单元T_DETECT_MEAN将构成心电信号ECG的T波的频率分量的功率转换为大致DC分量，并将转换的功率作为T波功率V_T输出。 R波功率V_R和T波功率V_T被输入到比较单元CMP，比较单元CMP输出R波功率V_R和T波功率V_T之间的幅度比较结果作为比较信号sig_comp 。
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公开(公告)号：US11546541B2
公开(公告)日：2023-01-03
申请号：US17189748
申请日：2021-03-02
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa
Abstract: A semiconductor device according to an embodiment includes a plurality of element arrays, a signal-processing circuit, and a comparison-voltage generation circuit. Each element array is selectively connected to a vertical signal line and includes an amplification transistor configured to output a first analog signal on the basis of an input analog voltage and an actual value of variation of a characteristic value of each element array included in the plurality of element arrays. The comparison-voltage generation circuit is configured to output a gradually increasing or gradually decreasing comparison voltage. The signal-processing circuit includes a storage circuit and is configured to compare the first analog signal with the comparison voltage and store a timing at which the comparison voltage and a value of a second analog signal generated by adding a predetermined absolute value to the first analog signal match each other onto the storage circuit.
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Patent Agency Ranking
公开(公告)号：US20210185254A1
公开(公告)日：2021-06-17
申请号：US17190838
申请日：2021-03-03
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa , Keisuke Ogawa
Abstract: In an imaging system according to an embodiment, a camera unit and an information-processing unit are connected to each other by differential-signal transmission lines. The camera unit includes a solid-state imaging device and an output driver. The solid-state imaging device is configured to operate on the basis of a power source voltage higher than a substrate voltage and generate imaging data. The output driver is configured to output a differential signal of the imaging data to the differential-signal transmission lines. The information-processing unit includes a voltage generator and a de-emphasis circuit. The voltage generator is configured to generate a reference voltage higher than the substrate voltage and lower than the power source voltage. The de-emphasis circuit is configured to control an amplitude of the differential signal by using the substrate voltage and the reference voltage.
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公开(公告)号：US20190020834A1
公开(公告)日：2019-01-17
申请号：US16136997
申请日：2018-09-20
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa
Abstract: A noise removing circuit includes a capacitor, a buffer circuit, and a switch. The capacitor includes a first terminal and a second terminal. The buffer circuit includes a third terminal and a fourth terminal. The switch sets the capacitor and the buffer circuit to be in one of a first state and a second state. In the first state, the first terminal is connected to the fourth terminal, a reference voltage is input to the second terminal, and the third terminal is connected to the signal source. In the second state, the first terminal is connected to the signal source, and the second terminal is connected to the third terminal.
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公开(公告)号：US20180358977A1
公开(公告)日：2018-12-13
申请号：US16106687
申请日：2018-08-21
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Shuzo Hiraide , Masato Osawa
IPC: H03M1/46
Abstract: In an AD converter, a first capacitor DAC circuit performs a first operation in parallel with a second operation by a second capacitor DAC circuit, and the first capacitor DAC circuit performs the second operation in parallel with the first operation by the second capacitor DAC circuit. Electric charge corresponding to an input signal is sampled in the first operation. AD conversions are sequentially performed on the basis of the electric charge sampled in each first capacitor included in a plurality of first capacitors or each second capacitor included in a plurality of second capacitors in the second operation. The first capacitor DAC circuit and the second capacitor DAC circuit alternately perform the first operation and the second operation.
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公开(公告)号：US09979364B2
公开(公告)日：2018-05-22
申请号：US15788505
申请日：2017-10-19
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa , Yasunari Harada , Hideki Kato
CPC classification number: H03F3/72 , H03F1/26 , H03F3/45475 , H03F2200/135 , H03F2200/213 , H03F2200/411 , H03F2200/45 , H03F2203/45514 , H03F2203/45551 , H03F2203/7231 , H03G1/0094 , H03G3/001 , H03M1/1245
Abstract: In a semiconductor device, a first variable gain amplifier and a second variable gain amplifier constitute a switched capacitor type variable gain amplifier. A selection switch switches connection among the first variable gain amplifier, the second variable gain amplifier, and a load circuit such that the first variable gain amplifier and the load circuit are connected to each other when an amplification factor of the first variable gain amplifier is a predetermined gain or less, and the second variable gain amplifier is connected between the first variable gain amplifier and the load circuit when the amplification factor of the first variable gain amplifier is larger than the predetermined gain.
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公开(公告)号：US11258990B2
公开(公告)日：2022-02-22
申请号：US17190778
申请日：2021-03-03
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa
Abstract: In an imaging system according to an embodiment of the present invention, a camera unit is configured to transmit imaging data to an information-processing unit as a downlink packet. The camera unit is configured to hold predetermined data in the imaging data as a transmission key. The information-processing unit is configured to receive the downlink packet, recognize the predetermined data in the imaging data as the transmission key, and generate a reception key on the basis of the transmission key. The information-processing unit is configured to transmit an uplink packet including the reception key and a register-setting signal indicating an imaging condition to the camera unit. The camera unit is configured to write the register-setting signal received with the reception key in a register when the transmission key and the reception key meet a predetermined condition.
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