公开(公告)号：US07209390B2

公开(公告)日：2007-04-24

申请号：US10876378

申请日：2004-06-24

Applicant: Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

Inventor： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

IPC: G11C16/00

CPC classification number: G11C16/3481 ,  G11C16/0466 ,  G11C16/3436

Abstract: A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles. The charge retention properties can be greatly improved by these refill cycles.

Abstract translation: 具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。 充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。 该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。 通过这些再填充循环可以大大提高电荷保持性。

公开(公告)号：US07209385B1

公开(公告)日：2007-04-24

申请号：US11327561

申请日：2006-01-06

Applicant: Chao-I Wu ,  Ming Hsiu Lee ,  Ming-Chang Kuo

Inventor： Chao-I Wu ,  Ming Hsiu Lee ,  Ming-Chang Kuo

IPC: G11C16/04

CPC classification number: G11C16/0491 ,  G11C16/0466 ,  G11C16/14 ,  H01L21/28282 ,  H01L29/792

Abstract: An Assisted Charge (AC) Memory cell comprises a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The gate electrode can comprise a trapping structure. The trapping structure can be treated as electrically split into two sides. One side can be referred to as the “AC-side” and can be fixed at a high voltage by trapping electrons within the structure. The electrons are referred to as assisted charges. The other side of can be used to store data and is referred to as the “data-side.” The abrupt electric field between AC-side and the data-side can enhance programming efficiency.

Abstract translation: 辅助充电（AC）存储单元包括晶体管，其包括例如p型衬底，其具有n +源极区域和n +漏极区域注入在p型衬底上。 栅电极可以形成在衬底上以及源区和漏区的部分之上。 栅电极可以包括捕获结构。 捕获结构可以被电分为两侧。 一侧可以称为“AC侧”，并且可以通过在结构内捕获电子而将其固定在高电压。 电子被称为辅助电荷。 另一边可以用来存储数据，被称为“数据端”。 AC侧和数据侧之间的突发电场可以提高编程效率。

公开(公告)号：US20070025153A1

公开(公告)日：2007-02-01

申请号：US11161359

申请日：2005-08-01

Applicant: Chao-I Wu ,  Ming-Hsiu Lee

Inventor： Chao-I Wu ,  Ming-Hsiu Lee

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/0475 ,  G11C16/18

Abstract: A method of operating a non-volatile memory is provided, wherein the non-volatile memory at least includes: a gate structure formed by stacking a tunneling dielectric layer, charge trapping layer, a dielectric layer and a gate conducting layer sequentially, and a source region and a drain region. When the operating method is carried out, a ultraviolet is irradiated to the non-volatile memory to inject electrons into the charge trapping layer to erase the non-volatile memory, and a negative voltage is applied to the gate conductive layer and a positive voltage is applied to the drain region to program the non-volatile memory by band-to-band induced hot hole injection.

Abstract translation: 提供了一种操作非易失性存储器的方法，其中非易失性存储器至少包括：通过层叠隧穿介电层，电荷俘获层，电介质层和栅极导电层顺序地形成的栅极结构，以及源极 区域和漏极区域。 当执行操作方法时，紫外线照射到非易失性存储器以将电子注入电荷捕获层以擦除非易失性存储器，并且向栅极导电层施加负电压，并且正电压为 施加到漏极区域以通过频带带诱导的热空穴注入对非易失性存储器进行编程。

公开(公告)号：US07139200B2

公开(公告)日：2006-11-21

申请号：US10873623

申请日：2004-06-23

Applicant: Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

Inventor： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

IPC: G11C11/34

CPC classification number: G11C16/0475

Abstract: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

公开(公告)号：US20060146613A1

公开(公告)日：2006-07-06

申请号：US11026799

申请日：2004-12-30

Applicant: Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

Inventor： Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

IPC: G11C16/04

CPC classification number: G11C11/5671 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3459 ,  G11C16/3481

Abstract: A method for programming one or more memory cells is disclosed. The one or more memory cells need to be two sides operated. After verifying both sides of each memory cell to identify the sides of the memory cells to be programmed, a programming voltage pulse is given to the first sides of the memory cells identified to be programmed. Another verification process is performed for both sides of each memory cell to identify the sides of the memory cells to be programmed. Next, a programming voltage pulse is given to the second sides of the memory cells identified to be programmed. The verifying both sides, programming the first sides, verifying both sides, and programming the second sides will continue until the both sides of each memory cell are programmed to a target programming voltage. The target programming voltage might have multiple voltage levels.

Abstract translation: 公开了一种用于编程一个或多个存储器单元的方法。 一个或多个存储单元需要是双面操作的。 在验证每个存储器单元的两侧以识别待编程的存储器单元的侧面之后，将编程电压脉冲提供给被识别为被编程的存储器单元的第一侧。 对每个存储单元的两侧执行另一个验证过程，以识别待编程的存储器单元的侧面。 接下来，将编程电压脉冲提供给被识别为被编程的存储器单元的第二侧。 验证两侧，编程第一面，验证双面，并对第二面进行编程将一直持续到每个存储单元的两侧都编程为目标编程电压。 目标编程电压可能有多个电压电平。

公开(公告)号：US20060104105A1

公开(公告)日：2006-05-18

申请号：US10991537

申请日：2004-11-17

Applicant: Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Hsiang-Lan Lung

Inventor： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Hsiang-Lan Lung

IPC: G11C17/00

CPC classification number: G11C16/12 ,  G11C16/0475 ,  G11C16/26

Abstract: A method of determining an optimal reading voltage for reading a two-side non-volatile memory programmed with a threshold voltage Vt is described. A first side of a memory cell is programmed to Vt, and then an I1-Vg curve of the first side and an I2-Vg curve of the second side are measured, wherein Vg is the gate voltage. A Gm1-Vg curve and a Gm2-Vg curve are plotted, wherein Gm1=dI1/dVg and Gm2=dI2/dVg. The optimal reading voltage VgO is determined as the gate voltage at the intersection of Gm1 and Gm2, corresponding to a maximal total current window Wm(=I2(VgO)−I1(VgO)).

Abstract translation: 描述了一种确定用于读取用阈值电压Vt编程的双侧非易失性存储器的最佳读取电压的方法。 存储器单元的第一侧被编程为Vt，然后第二侧的I 1 -T 1 -V G曲线和第二侧的I 2 -V -V曲线是 测量，其中Vg是栅极电压。 绘制了一个Gm 1-ΔVg曲线和一个Gm 2 -V -G曲线，其中G m 1 = 1/1 / / dVg和Gm2 = dI2 / dVg。 确定最佳读取电压V g O O N作为在最大总电流窗口Gm1和Gm2的交点处的栅极电压 Wm（= I 2）（V g O O） - I 1（V g O O））。

公开(公告)号：US20050237816A1

公开(公告)日：2005-10-27

申请号：US10876378

申请日：2004-06-24

Applicant: Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

Inventor： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

IPC: G11C11/36 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/3481 ,  G11C16/0466 ,  G11C16/3436

Abstract: A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles.

Abstract translation: 具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。 充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。 该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。

公开(公告)号：US20050116910A1

公开(公告)日：2005-06-02

申请号：US10919558

申请日：2004-08-16

Applicant: Ming-Hsiu Lee ,  Scott Jen

Inventor： Ming-Hsiu Lee ,  Scott Jen

IPC: G02F3/00 ,  G09G3/36 ,  G09G5/00

CPC classification number: G09G3/3648 ,  G09G2320/0693

Abstract: A video regulating module and method for mitigating flicker of an LCD device, wherein the method has acts of: supplying a pure color signal contained with brightness and gray scale information to the LCD device; measuring optical characteristics of the LCD device; generating compensating parameters directed to the pure color signal; and storing the compensating parameters in the LCD device. Therefore, when a video signal is input to the LCD device, the stored compensating parameters are applied to compensate the video signal to eliminate the flicker problem and obtain superior image quality.

Abstract translation: 一种用于减轻LCD装置的闪烁的视频调节模块和方法，其中该方法具有以下动作：将包含亮度和灰度信息的纯色信号提供给LCD装置; 测量LCD设备的光学特性; 生成针对纯色信号的补偿参数; 并将补偿参数存储在LCD装置中。 因此，当将视频信号输入到LCD装置时，应用所存储的补偿参数来补偿视频信号以消除闪烁问题并获得优异的图像质量。

公开(公告)号：US20050062079A1

公开(公告)日：2005-03-24

申请号：US10605253

申请日：2003-09-18

Applicant: Chao-I Wu ,  Ming-Hsiu Lee

Inventor： Chao-I Wu ,  Ming-Hsiu Lee

IPC: H01L21/336 ,  H01L27/10

CPC classification number: H01L27/10

Abstract: A method for forming a PN junction is described. A stacked structure consisting of an N-doped (or P-doped) layer, a dielectric layer and a nucleation layer is formed, and then an insulating layer is formed having an opening therein. A P-doped (or N-doped) polysilicon or amorphous silicon layer is filled into the opening, and then annealed to convert into a single-crystal silicon layer. Then, the dielectric layer is broken down to form a PN junction.

Abstract translation: 描述了形成PN结的方法。 形成由N掺杂（或P掺杂）层，电介质层和成核层组成的堆叠结构，然后形成其中具有开口的绝缘层。 将p掺杂（或N掺杂）多晶硅或非晶硅层填充到开口中，然后退火以转化为单晶硅层。 然后，介电层被分解以形成PN结。

公开(公告)号：US08891293B2

公开(公告)日：2014-11-18

申请号：US13472395

申请日：2012-05-15

Applicant: Pei-Ying Du ,  Chao-I Wu ,  Ming-Hsiu Lee ,  Sangbum Kim ,  Chung Hon Lam

Inventor： Pei-Ying Du ,  Chao-I Wu ,  Ming-Hsiu Lee ,  Sangbum Kim ,  Chung Hon Lam

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0021

Abstract: Phase change based memory devices and methods for operating such devices described herein overcome the set or reset failure mode and result in improved endurance, reliability and data storage performance. A high current repair operation is carried out in response to a set or reset failure of a phase change memory cell. The higher current repair operation can provide a sufficient amount of energy to reverse compositional changes in the phase change material which can occur after repeated set and reset operations. By reversing these compositional changes, the techniques described herein can recover a memory cell which experienced a set or reset failure, thereby extending the endurance of the memory cell. In doing so, phase change based memory devices and methods for operating such devices are provided which have high cycle endurance.

Abstract translation: 基于相变的存储器件和用于操作这里描述的这种器件的方法克服了设置或复位故障模式并导致改进的耐久性，可靠性和数据存储性能。 响应于相变存储单元的置位或复位故障执行高电流修复操作。 更高的电流修复操作可以提供足够的能量来反转在重复设置和复位操作之后可能发生的相变材料的组成变化。 通过颠倒这些组合变化，本文描述的技术可以恢复经历设置或复位故障的存储器单元，从而延长存储单元的耐久性。 这样做，提供了具有高循环耐久性的基于相变的存储器件和用于操作这些器件的方法。