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公开(公告)号：US5726498A
公开(公告)日：1998-03-10
申请号：US451873
申请日：1995-05-26
IPC分类号： H01L23/522 , H01L23/528 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5222 , H01L23/5283 , H01L2924/0002
摘要： Capacitive coupling, and attendant cross-talk, is reduced by increasing the distance between wire surfaces in integrated circuit applications. This is done by changing wire shape from the conventional rectangular cross-section. A cross-section which consists of a rectangular portion and a shaped, triangular portion is created, having the effect of increasing the effective distance between adjacent conductors. Cross-sectional area of wires is maintained and thus the current carrying capacity is maintained. The wire shapes may be produced using several alternate methods.
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公开(公告)号：US08518767B2
公开(公告)日：2013-08-27
申请号：US11680221
申请日：2007-02-28
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66818
摘要： Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.
摘要翻译： 本发明的实施例提供了Fin场效应晶体管（FinFET）中的相对均匀的宽度鳍片及其形成方法。 翅片结构可以形成为使翅片结构的侧壁部分的表面垂直于第一结晶方向。 翅片结构端部的锥形区域可以垂直于第二晶体方向。 可以对翅片结构进行晶体依赖蚀刻。 晶体依赖蚀刻可以相对较快地从第二晶体方向垂直于翅片的部分去除材料，从而形成相对均匀的宽度鳍片结构。
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公开(公告)号：US20120146112A1
公开(公告)日：2012-06-14
申请号：US13396291
申请日：2012-02-14
IPC分类号： H01L29/772
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66818
摘要： Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.
摘要翻译： 本发明的实施例提供了Fin场效应晶体管（FinFET）中的相对均匀的宽度鳍片及其形成方法。 翅片结构可以形成为使翅片结构的侧壁部分的表面垂直于第一结晶方向。 翅片结构端部的锥形区域可以垂直于第二晶体方向。 可以对翅片结构进行晶体依赖蚀刻。 晶体依赖蚀刻可以相对较快地从第二晶体方向垂直于翅片的部分去除材料，从而形成相对均匀的宽度鳍片结构。
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114.发明授权Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods 失效使用多孔层形成绝缘体上半导体结构的方法和通过这些方法形成的半导体结构的方法公开(公告)号：US07767541B2
公开(公告)日：2010-08-03
申请号：US11259297
申请日：2005-10-26
CPC分类号： H01L21/76251 , H01L21/76245 , Y10S438/933
摘要： A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.
摘要翻译： 一种半导体结构，其包括单晶含锗层，优选基本上纯的锗，衬底和将锗含量层与衬底分离的掩埋绝缘体层。 在基板上形成可以是多孔硅的多孔层，在多孔硅层上形成含锗层。 多孔层可以转化成一层氧化物，这提供了埋层绝缘体层。 或者，含锗层可以从多孔层转移到另一衬底上的绝缘层。 在转移之后，绝缘层被埋在后面的衬底和含锗层之间。
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115.发明授权公开(公告)号：US07737530B2
公开(公告)日：2010-06-15
申请号：US12130176
申请日：2008-05-30
IPC分类号： H01L29/732
CPC分类号： H01L29/732 , H01L29/66265
摘要： Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure includes a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further includes a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body.
摘要翻译： 用于双极结晶体管的半导体器件结构和制造这种半导体器件结构的方法。 半导体器件结构包括具有顶表面和从顶表面延伸到绝缘层的侧壁的半导体本体，包括具有第一导电类型的第一半导体材料的第一区域和包括具有第二导电类型的第二半导体材料的第二区域 导电类型。 第一和第二区域各自延伸穿过半导体本体的顶表面和侧壁。 器件结构还包括限定在第一和第二区域之间并且跨越半导体本体的顶表面和侧壁延伸的结。
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116.发明授权Semiconductor device structures incorporating voids and methods of fabricating such structures 有权包含空隙的半导体器件结构和制造这种结构的方法公开(公告)号：US07691712B2
公开(公告)日：2010-04-06
申请号：US11425588
申请日：2006-06-21
IPC分类号： H01L21/8234
CPC分类号： H01L29/4983 , H01L21/823807 , H01L21/823864 , H01L29/4991 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor device structures and fabrication methods for field effect transistors in which a gate electrode is provided with an air gap or void disposed adjacent to a sidewall of the gate electrode. The void may be bounded by a dielectric spacer proximate to the sidewall of the gate electrode and a dielectric layer having a spaced relationship with the dielectric spacer. The methods of the invention involve the use of a temporary spacer consisting of a sacrificial material supplied adjacent to the sidewall of the gate electrode, which is removed after the dielectric layer is formed.
摘要翻译： 用于场效应晶体管的半导体器件结构和制造方法，其中栅电极设置有与栅电极的侧壁相邻设置的气隙或空隙。 空隙可以由靠近栅电极的侧壁的电介质隔离物和与电介质间隔物具有间隔关系的电介质层界定。 本发明的方法涉及使用由邻近栅电极的侧壁提供的牺牲材料组成的临时间隔物，其在形成介电层之后被去除。
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117.发明授权Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby 有权使用心轴制造半导体结构的方法和由此形成的半导体结构公开(公告)号：US07638381B2
公开(公告)日：2009-12-29
申请号：US11246830
申请日：2005-10-07
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/00 , H01L21/84 , H01L21/3205
CPC分类号： H01L29/785 , H01L29/66795
摘要： Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selective to the monocrystalline silicon of the body. The mandrel may be composed of porous silicon and the body may be fabricated using either a semiconductor-on-insulator substrate or a bulk substrate. The body may be used to fabricate a fin body of a fin-type field effect transistor.
摘要翻译： 制造半导体结构的方法，其中在牺牲心轴的侧壁上形成单晶硅体，并通过该方法制造半导体结构。 在形成单晶硅体之后，心轴的牺牲材料被选择性地去除到主体的单晶硅上。 心轴可以由多孔硅组成，并且主体可以使用绝缘体上半导体衬底或块状衬底来制造。 本体可用于制造翅片型场效应晶体管的翅片体。
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118.发明授权公开(公告)号：US07618872B2
公开(公告)日：2009-11-17
申请号：US12125342
申请日：2008-05-22
IPC分类号： H01L21/331
CPC分类号： H01L29/732 , H01L29/66265
摘要： Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure comprises a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further comprises a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body.
摘要翻译： 用于双极结晶体管的半导体器件结构和制造这种半导体器件结构的方法。 半导体器件结构包括具有顶表面和从顶表面延伸到绝缘层的侧壁的半导体本体，包括具有第一导电类型的第一半导体材料的第一区域和包括具有第二导电类型的第二半导体材料的第二区域 导电类型。 第一和第二区域各自延伸穿过半导体本体的顶表面和侧壁。 器件结构还包括限定在第一和第二区域之间并且跨越半导体本体的顶表面和侧壁延伸的接合部。
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119.发明授权Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures 失效体接触半导体结构和制造这种体接触半导体结构的方法公开(公告)号：US07608506B2
公开(公告)日：2009-10-27
申请号：US11925352
申请日：2007-10-26
IPC分类号： H01L21/4763
CPC分类号： H01L21/84 , H01L27/0218 , H01L27/10841 , H01L27/1203 , H01L29/66545
摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.
摘要翻译： 一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括建立在绝缘体上半导体（SOI）晶片上的多个垂直存储单元和SOI晶片的埋入介质层中的体接触。 体接触将半导体本体与一个垂直存储单元的存取器件的沟道区和SOI晶片的半导体衬底电耦合。 身体接触提供了一种电流泄漏路径，可减少浮体对垂直记忆体的影响。 体接触可以通过离子注入工艺形成，该方法改变掩埋介电层的区域的化学计量，使得改性区域以相对较高的电阻变为导电性。
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公开(公告)号：US07560784B2
公开(公告)日：2009-07-14
申请号：US11669970
申请日：2007-02-01
IPC分类号： H01L29/76
CPC分类号： H01L29/868 , H01L29/0649 , H01L29/417 , H01L29/66136
摘要： Embodiments of the invention generally relate to the field of semiconductor devices, and more specifically to fin-based junction diodes. A portion of a doped semiconductor fin may protrude through a first doped layer. An intrinsic layer may be disposed on the protruding semiconductor fin. A second semiconductor layer may be disposed on the intrinsic layer, thereby forming a PIN diode compatible with FinFET technology and having increased junction area.
摘要翻译： 本发明的实施例一般涉及半导体器件的领域，更具体地涉及翅片型结二极管。 掺杂半导体鳍片的一部分可以突出穿过第一掺杂层。 本征层可以设置在突出的半导体鳍片上。 第二半导体层可以设置在本征层上，从而形成与FinFET技术兼容并具有增加的结面积的PIN二极管。
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