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    Semiconductor structures with body contacts and fabrication methods thereof
    2.
    发明授权
    Semiconductor structures with body contacts and fabrication methods thereof 有权
    具有身体接触的半导体结构及其制造方法

    公开(公告)号：US07611931B2

    公开(公告)日：2009-11-03

    申请号：US11928135

    申请日：2007-10-30

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack Allan Mandelman

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack Allan Mandelman

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/1203 ,  H01L27/0218 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10891

    摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.

    摘要翻译： 一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括构建在绝缘体上半导体（SOI）晶片上的多个垂直存储器单元和电耦合SOI的半导体本体和半导体衬底的主体接触 晶圆。 半导体本体包括用于垂直存储单元之一的存取装置的通道区域。 延伸穿过SOI晶片的掩埋介电层的主体接触件提供电流泄漏路径，其减少浮体对垂直存储单元的影响。 可以通过蚀刻延伸穿过SOI晶片的半导体主体和埋入介质层的通孔来形成本体接触，并且延伸到衬底中并且用导电材料部分地填充通孔，所述导电材料使半导体本体与衬底电耦合。

    Integrated Fin-Local Interconnect Structure
    3.
    发明申请
    Integrated Fin-Local Interconnect Structure 审中-公开
    集成鳍局部互连结构

    公开(公告)号：US20090007036A1

    公开(公告)日：2009-01-01

    申请号：US11925387

    申请日：2007-10-26

    申请人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： G06F9/45

    CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

    摘要： Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices, and more specifically to interconnecting semiconductor devices. A silicide layer may be formed on selective areas of a fin structure connecting one or more semiconductor devices or semiconductor device components. By providing silicided fin structures to locally interconnect semiconductor devices, the use of metal contacts and metal layers may be obviated, thereby allowing formation of smaller, less complex circuits.

    摘要翻译： 本发明的实施例一般涉及半导体器件的方法，系统和设计结构，更具体地涉及互连半导体器件。 可以在连接一个或多个半导体器件或半导体器件部件的翅片结构的选择性区域上形成硅化物层。 通过提供硅化物翅片结构来局部互连半导体器件，可以避免使用金属触点和金属层，从而形成较小的，较不复杂的电路。

    METHODS FOR FORMING GERMANIUM-ON-INSULATOR SEMICONDUCTOR STRUCTURES USING A POROUS LAYER AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS
    4.
    发明申请
    METHODS FOR FORMING GERMANIUM-ON-INSULATOR SEMICONDUCTOR STRUCTURES USING A POROUS LAYER AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS 有权
    使用这种方法形成多孔层和半导体结构形成绝缘体绝缘体半导体结构的方法

    公开(公告)号：US20080211054A1

    公开(公告)日：2008-09-04

    申请号：US12120455

    申请日：2008-05-14

    申请人： Kangguo Cheng ,  Brian Joseph Greene ,  Jack Allan Mandelman

    发明人： Kangguo Cheng ,  Brian Joseph Greene ,  Jack Allan Mandelman

    IPC分类号： H01L29/16

    CPC分类号： H01L21/76251 ,  H01L21/76245 ,  Y10S438/933

    摘要： A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.

    摘要翻译： 一种半导体结构，其包括单晶含锗层，优选基本上纯的锗，衬底和将锗含量层与衬底分离的掩埋绝缘体层。 在基板上形成可以是多孔硅的多孔层，在多孔硅层上形成含锗层。 多孔层可以转化成一层氧化物，这提供了埋层绝缘体层。 或者，含锗层可以从多孔层转移到另一衬底上的绝缘层。 在转移之后，绝缘层被埋在后面的衬底和含锗层之间。

    Hybrid Field Effect Transistor and Bipolar Junction Transistor Structures and Methods for Fabricating Such Structures
    5.
    发明申请
    Hybrid Field Effect Transistor and Bipolar Junction Transistor Structures and Methods for Fabricating Such Structures 审中-公开
    混合场效应晶体管和双极结晶体管结构和制造这种结构的方法

    公开(公告)号：US20080001234A1

    公开(公告)日：2008-01-03

    申请号：US11427962

    申请日：2006-06-30

    申请人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    发明人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    IPC分类号： H01L29/76

    CPC分类号： H01L29/732 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/12 ,  H01L29/66265 ,  H01L29/785

    摘要： Semiconductor device structures that integrate field effect transistors and bipolar junction transistors on a single substrate, such as a semiconductor-on-insulator substrate, and methods for fabricating such hybrid semiconductor device structures. The field effect and bipolar junction transistors are fabricated using adjacent electrically-isolated semiconductor bodies. During fabrication of the device structures, certain fabrication stages strategically rely on block masks for process isolation. Other fabrication stages are shared during the fabrication process for seamless integration that reduces process complexity.

    摘要翻译： 在诸如绝缘体上半导体衬底的单个衬底上集成场效应晶体管和双极结型晶体管的半导体器件结构以及用于制造这种混合半导体器件结构的方法。 使用相邻的电隔离半导体器件制造场效应和双极结晶体管。 在器件结构的制造过程中，某些制造阶段有策略地依靠块掩模来进行过程隔离。 其他制造阶段在无缝集成的制造过程中共享，从而降低了工艺复杂性。

    Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods
    6.
    发明授权
    Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods 有权
    使用多孔层形成绝缘体上半导体结构的方法和通过这些方法形成的半导体结构的方法

    公开(公告)号：US07928436B2

    公开(公告)日：2011-04-19

    申请号：US12120455

    申请日：2008-05-14

    申请人： Kangguo Cheng ,  Brian Joseph Greene ,  Jack Allan Mandelman

    发明人： Kangguo Cheng ,  Brian Joseph Greene ,  Jack Allan Mandelman

    IPC分类号： H01L29/04 ,  H01L29/10

    CPC分类号： H01L21/76251 ,  H01L21/76245 ,  Y10S438/933

    摘要： A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.

    摘要翻译： 一种半导体结构，其包括单晶含锗层，优选基本上纯的锗，衬底和将锗含量层与衬底分离的掩埋绝缘体层。 在基板上形成可以是多孔硅的多孔层，在多孔硅层上形成含锗层。 多孔层可以转化成一层氧化物，这提供了埋层绝缘体层。 或者，含锗层可以从多孔层转移到另一衬底上的绝缘层。 在转移之后，绝缘层被埋在后面的衬底和含锗层之间。

    Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures
    7.
    发明授权
    Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures 失效
    具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法

    公开(公告)号：US07898014B2

    公开(公告)日：2011-03-01

    申请号：US11393142

    申请日：2006-03-30

    申请人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    发明人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10841 ,  H01L27/10864

    摘要： Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type. Methods for forming the doped regions involve depositing either a layer of a material doped with both dopants or different layers each doped with one of the dopants in the trench and, then, diffusing the dopants from the layer or layers into the semiconductor material bordering the trench sidewall.

    摘要翻译： 具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法。 半导体结构包括限定在与沟槽的侧壁相邻的衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。 半导体材料的中间区域分离第一和第二掺杂区域。 第三掺杂区域限定在与沟槽的侧壁接壤并且设置在第一和第二掺杂区域之间的半导体材料中。 第三掺杂区被掺杂以具有与第一导电类型相反的第二导电类型。 用于形成掺杂区域的方法包括沉积掺杂有掺杂剂或不同层的材料的层，每个掺杂剂或不同的层在沟槽中掺杂有一种掺杂剂，然后将掺杂剂从层或层扩散到与沟槽接壤的半导体材料 侧壁。

    SEMICONDUCTOR DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATING SUCH STRUCTURES
    9.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATING SUCH STRUCTURES 失效
    双极晶体管的半导体器件结构和制作这种结构的方法

    公开(公告)号：US20080220583A1

    公开(公告)日：2008-09-11

    申请号：US12125342

    申请日：2008-05-22

    申请人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    发明人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    IPC分类号： H01L21/331

    CPC分类号： H01L29/732 ,  H01L29/66265

    摘要： Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure comprises a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further comprises a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body.

    摘要翻译： 用于双极结晶体管的半导体器件结构和制造这种半导体器件结构的方法。 半导体器件结构包括具有顶表面和从顶表面延伸到绝缘层的侧壁的半导体本体，包括具有第一导电类型的第一半导体材料的第一区域和包括具有第二导电类型的第二半导体材料的第二区域 导电类型。 第一和第二区域各自延伸穿过半导体本体的顶表面和侧壁。 器件结构还包括限定在第一和第二区域之间并且跨越半导体本体的顶表面和侧壁延伸的接合部。

    Method for Reducing Defects in Buried Oxide Layers of Silicon on Insulator Substrates
    10.
    发明申请
    Method for Reducing Defects in Buried Oxide Layers of Silicon on Insulator Substrates 审中-公开
    减少硅绝缘体衬底氧化层缺陷的方法

    公开(公告)号：US20080048259A1

    公开(公告)日：2008-02-28

    申请号：US11466480

    申请日：2006-08-23

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    IPC分类号： H01L27/12

    CPC分类号： H01L29/78603 ,  H01L29/66772 ,  H01L29/78609

    摘要： A method and a structure for reducing defects in buried oxide layers of a silicon-on-insulator substrate. The method includes: generating a beam of infrared radiation of a selected wavelength; exposing a silicon-on-insulator substrate to the beam of infrared radiation, the substrate comprising a buried silicon dioxide layer between a lower layer of silicon and an upper layer of silicon; and wherein silicon has a transmittance of at least 95% at the selected wavelength and silicon dioxide has a transmittance of less than 80% at the selected wavelength.

    摘要翻译： 一种减少绝缘体上硅衬底的掩埋氧化物层缺陷的方法和结构。 该方法包括：产生所选波长的红外辐射束; 将绝缘体上硅衬底暴露于所述红外辐射束，所述衬底包括在下层硅和硅上层之间的掩埋二氧化硅层; 并且其中硅在所选波长处具有至少95％的透射率，并且二氧化硅在所选择的波长处具有小于80％的透射率。