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    COMPLETING MIDDLE OF LINE INTEGRATION ALLOWING FOR SELF-ALIGNED CONTACTS
    111.
    发明申请
    COMPLETING MIDDLE OF LINE INTEGRATION ALLOWING FOR SELF-ALIGNED CONTACTS 有权
    完成自对准联系人允许的线路集成中间

    公开(公告)号：US20150041909A1

    公开(公告)日：2015-02-12

    申请号：US13961318

    申请日：2013-08-07

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche ,  Haiting Wang

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

    Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET having complete middle of line integration. Specifically, a hard mask layer and set of spacers are removed from the gate stacks leaving behind (among other things) a set of dummy gates. A liner layer is formed over the set of dummy gates and over a source-drain region adjacent to the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates and the source-drain region. An inter-layer dielectric (ILD) is then deposited over the set of dummy gates and over the source-drain region, and the set of dummy gates are then removed. The result is an environment in which a self-aligned contact to the source-drain region can be deposited.

    Abstract translation: 通常，本发明的各方面涉及用于形成半导体器件的方法，例如具有完全中线整合的FET。 具体来说，硬掩模层和一组间隔物从栅极堆叠中移除，留下（尤其是）一组虚拟栅极。 衬套层形成在该组虚拟栅极之上并且与该组虚拟栅极相邻的源极 - 漏极区域上方。 然后将衬套层从该组虚拟栅极和源极 - 漏极区域的顶表面（或其至少一部分）移除。 然后将层间电介质（ILD）沉积在该组虚拟栅极上并在源极 - 漏极区域上方，然后去除该组虚拟栅极。 结果是可以沉积与源极 - 漏极区域的自对准接触的环境。

    Self-aligned cuts in an interconnect structure
    112.
    发明授权
    Self-aligned cuts in an interconnect structure 有权

    公开(公告)号：US10685874B1

    公开(公告)日：2020-06-16

    申请号：US16220565

    申请日：2018-12-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Hui Zang ,  Lei Sun ,  Lars Liebmann ,  Daniel Chanemougame ,  Guillaume Bouche

    IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

    Abstract: Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.

    METHOD OF PATTERNING TARGET LAYER
    114.
    发明申请
    METHOD OF PATTERNING TARGET LAYER 审中-公开

    公开(公告)号：US20190303525A9

    公开(公告)日：2019-10-03

    申请号：US15791210

    申请日：2017-10-23

    Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

    Inventor： Syed Muhammad Yasser Sherazi ,  Guillaume Bouche ,  Julien Ryckaert

    IPC: G06F17/50 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L21/84 ,  H01L27/02 ,  H01L27/11 ,  H01L27/12

    Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method. In one aspect, a method of defining routing tracks in a target layer over a standard cell semiconductor device includes forming mandrels and forming a first set and a second set of spacers for defining the routing tracks. The standard cell semiconductor device includes a device layer and the routing tracks for contacting a device layer. The routing tracks include at least two pairs of off-center routing tracks, a central routing track arranged between the pairs of off-center routing tracks, and at least two edge tracks arranged on opposing sides of the at least two pairs of off-center routing tracks. A minimum distance between an off-center routing track and the central routing track next to the off-center routing track is smaller than a minimum distance between adjacent off-center routing tracks.

    METHODS OF PATTERNING DIELECTRIC LAYERS FOR METALLIZATION AND RELATED STRUCTURES
    115.
    发明申请
    METHODS OF PATTERNING DIELECTRIC LAYERS FOR METALLIZATION AND RELATED STRUCTURES 审中-公开

    公开(公告)号：US20190229059A1

    公开(公告)日：2019-07-25

    申请号：US16369050

    申请日：2019-03-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche

    IPC: H01L23/538 ,  H01L23/522 ,  H01L21/768

    Abstract: Structures including metallization layers and metal lines, and methods of forming thereof. A patterning stack, a masking layer, and a spacer patterning layer are formed over a dielectric layer, and an opening is formed in the spacer patterning layer. First and second spacers are formed on a portion of the masking layer at sidewalls of an opening in the spacer patterning layer. The first spacer and the second spacer overlie and traverse first portions of the dummy line. After removing the spacer patterning layer and masking layer, second portions of the dummy line are removed to form a feature in the patterning stack that includes a first gap beneath the first spacer and a second gap beneath the second spacer. A metal line is formed in the dielectric layer using the feature, and includes cuts at the first gap and the second gap in the feature.

    Methods of patterning dielectric layers for metallization and related structures
    116.
    发明授权
    Methods of patterning dielectric layers for metallization and related structures 有权

    公开(公告)号：US10347583B1

    公开(公告)日：2019-07-09

    申请号：US15860193

    申请日：2018-01-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche

    IPC: H01L21/768 ,  H01L23/538 ,  H01L23/522

    Abstract: Structures including metallization layers and metal lines, and methods of forming thereof. A patterning stack, a masking layer, and a spacer patterning layer are formed over a dielectric layer, and an opening is formed in the spacer patterning layer. First and second spacers are formed on a portion of the masking layer at sidewalls of an opening in the spacer patterning layer. The first spacer and the second spacer overlie and traverse first portions of the dummy line. After removing the spacer patterning layer and masking layer, second portions of the dummy line are removed to form a feature in the patterning stack that includes a first gap beneath the first spacer and a second gap beneath the second spacer. A metal line is formed in the dielectric layer using the feature, and includes cuts at the first gap and the second gap in the feature.

    Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts
    118.
    发明授权
    Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts 有权

    公开(公告)号：US10002786B1

    公开(公告)日：2018-06-19

    申请号：US15379707

    申请日：2016-12-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Nicholas Vincent Licausi ,  Guillaume Bouche

    IPC: H01L21/768 ,  H01L21/033 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

    Abstract: A method includes providing a semiconductor structure having a mandrel layer and a hardmask layer disposed above a dielectric layer. A mandrel cell is patterned into the mandrel layer. An opening is etched into the hardmask layer. The opening is self-aligned with a sidewall of the mandrel. A refill layer is disposed over the structure and recessed down to a level that is below a top surface of the hardmask layer to form an opening plug that covers a bottom of the opening. The mandrel cell is utilized to form a metal line cell into the dielectric layer, the metal line cell having metal lines and a minimum line cell pitch. The opening plug is utilized to form a continuity cut in a metal line of the metal line cell. The continuity cut has a length that is larger than the minimum line cell pitch.

    Interconnection lines having variable widths and partially self-aligned continuity cuts
    119.
    发明授权
    Interconnection lines having variable widths and partially self-aligned continuity cuts 有权

    公开(公告)号：US09887127B1

    公开(公告)日：2018-02-06

    申请号：US15379740

    申请日：2016-12-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Nicholas Vincent Licausi ,  Guillaume Bouche

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286

    Abstract: A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer. The metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines. The line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. The array of metal lines includes a signal line having a continuity cut disposed across its entire line width and a power line adjacent the signal line. The power line has a line width that is greater than twice the minimum line width. The power line has a notch disposed partially across its line width. The notch is aligned with the continuity cut in a direction perpendicular to the longitudinal direction of the metal lines.

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