公开(公告)号：US20080083949A1

公开(公告)日：2008-04-10

申请号：US11538560

申请日：2006-10-04

申请人： Huilong Zhu ,  Zhijiong Luo

发明人： Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L27/12

CPC分类号： H01L29/78615

摘要： A semiconductor structure includes a metal oxide semiconductor field effect transistor that includes a body contact region that extends from body region located beneath a channel region that separates a pair of source/drain regions within the metal oxide semiconductor field effect transistor. The body contact region is recessed with respect to a surface of the channel region to avoid shorting between a body contact and the source/drain regions.

摘要翻译： 半导体结构包括金属氧化物半导体场效应晶体管，其包括从位于金属氧化物半导体场效应晶体管内的一对源极/漏极区域的沟道区域下方的体区延伸的体接触区域。 身体接触区域相对于沟道区域的表面凹陷，以避免体接触和源极/漏极区域之间的短路。

公开(公告)号：US20070298572A1

公开(公告)日：2007-12-27

申请号：US11850076

申请日：2007-09-05

申请人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

发明人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.

摘要翻译： 一种半导体结构及其形成方法。 首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域 区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。 然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

公开(公告)号：US20070281405A1

公开(公告)日：2007-12-06

申请号：US11421910

申请日：2006-06-02

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Brian L Tessier

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Brian L Tessier

IPC分类号： H01L21/338

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7845

摘要： Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor including a gate thereof; removing a portion of the intrinsically stressed material over the gate; removing at least a portion of the gate, allowing stress retained by the gate to be transferred to the channel; replacing (or refilling) the gate with a replacement gate; and removing the intrinsically stressed material. Removing and replacing the gate allows stress retained by the original gate to be transferred to the channel, with the replacement gate maintaining (memorizing) that situation. The methods do not damage the gate dielectric. A structure may include a transistor having a channel including a first stress that is one of a compressive and tensile and a gate including a second stress that is the other of compressive and tensile.

摘要翻译： 公开了用替换的栅极和相关结构来施加晶体管的沟道的方法。 一种方法可以包括在包括其栅极的晶体管上提供固有应力的材料; 在门上移除一部分本征应力材料; 去除栅极的至少一部分，允许由栅极保持的应力传递到通道; 用更换的门更换（或补充）门; 并去除本征应力材料。 拆卸和更换门允许原始闸门保持的应力传递到通道，替换闸门保持（记住）这种情况。 这些方法不会损坏栅极电介质。 结构可以包括具有通道的晶体管，该沟道包括作为压缩和拉伸之一的第一应力和包括另一个压缩和拉伸的第二应力的栅极。

公开(公告)号：US20070267753A1

公开(公告)日：2007-11-22

申请号：US11383965

申请日：2006-05-18

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.

摘要翻译： 公开了具有用于接触的大致L形硅化物元件的结构，半导体器件和方法。 基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。 在一个实施例中，该结构包括基本上为L形的硅化物元件，其包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面 直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。 触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。 可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

公开(公告)号：US20070010081A1

公开(公告)日：2007-01-11

申请号：US11160698

申请日：2005-07-06

申请人： Zhijiong Luo ,  Huilong Zhu

发明人： Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L21/4763 ,  H01L21/3205 ,  H01L21/336

CPC分类号： H01L29/4975 ,  H01L21/28097 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/78

摘要： A process is described for forming a fully multiple silicided gate for complementary MOSFET (CMOS) devices. A silicidation process is performed on a gate structure, which includes a gate material overlying a gate dielectric disposed on a substrate. A layer of insulating material is formed which covers the gate structure; the thickness of this layer is less at sidewalls of the gate structure than on a top surface of the gate structure. A portion of the layer of insulating material is then removed, so that the sidewalls of the gate structure are exposed. A layer of metal is formed which covers the gate structure so that the metal is in contact with the sidewalls of the gate structure. The silicidation process is then performed, in which a metal silicide is formed from the gate material and the metal; the gate material is thereby fully silicided.

摘要翻译： 描述了用于形成用于互补MOSFET（CMOS）器件的完全多个硅化栅的工艺。 对栅极结构进行硅化处理，栅极结构包括覆盖设置在衬底上的栅极电介质的栅极材料。 形成覆盖栅极结构的绝缘材料层; 在栅极结构的侧壁处，该层的厚度小于栅极结构的顶表面。 然后去除绝缘材料层的一部分，使得栅极结构的侧壁暴露。 形成覆盖栅极结构的金属层，使得金属与栅极结构的侧壁接触。 然后进行硅化处理，其中由栅极材料和金属形成金属硅化物; 因此栅极材料被完全硅化。

公开(公告)号：US20060244075A1

公开(公告)日：2006-11-02

申请号：US10908087

申请日：2005-04-27

申请人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

发明人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L29/76

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.

摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括场效应晶体管（FET），其具有设置在第一和第二源极/漏极（S / D）延伸区域之间的沟道区域，第一和第二源极/漏极（S / D）延伸区域又分别与第一和第二S / D区域直接物理接触。 形成第一和第二硅化物区域，使得第一硅化物区域与第一S / D区域和第一S / D延伸区域直接物理接触，而第二硅化物区域与第二S / D区域直接物理接触 区域和第二S / D扩展区域。 对于与第一S / D延伸区域接触的区域，第一硅化物区域比与第一S / D区域接触的区域更薄。 类似地，对于与第二S / D延伸区域接触的区域，第二硅化物区域比与第二S / D区域接触的区域更薄。

公开(公告)号：US09543188B2

公开(公告)日：2017-01-10

申请号：US13142378

申请日：2011-03-02

申请人： Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu ,  Huicai Zhong

发明人： Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu ,  Huicai Zhong

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L21/76232 ,  H01L21/823481

摘要： The present invention provides an isolation structure for a semiconductor substrate and a method for manufacturing the same, as well as a semiconductor device having the structure. The present invention relates to the field of semiconductor manufacture. The isolation structure comprises: a trench embedded in a semiconductor substrate; an oxide layer covering the bottom and sidewalls of the trench, and isolation material in the trench and on the oxide layer, wherein a portion of the oxide layer on an upper portion of the sidewalls of the trench comprises lanthanum-rich oxide. By the trench isolation structure according to the present invention, metal lanthanum in the lanthanum-rich oxide can diffuse into corners of the oxide layer of the gate stack, thus alleviating the impact of the narrow channel effect and making the threshold voltage adjustable.

摘要翻译： 本发明提供一种用于半导体衬底的隔离结构及其制造方法，以及具有该结构的半导体器件。 本发明涉及半导体制造领域。 隔离结构包括：嵌入在半导体衬底中的沟槽; 覆盖沟槽的底部和侧壁的氧化物层，以及沟槽和氧化物层上的隔离材料，其中沟槽侧壁上部的氧化物层的一部分包括富镧氧化物。 通过根据本发明的沟槽隔离结构，富镧氧化物中的金属镧可以扩散到栅极堆叠的氧化物层的角部，从而减轻窄沟道效应的影响并使阈值电压可调。

公开(公告)号：US09496178B2

公开(公告)日：2016-11-15

申请号：US13634266

申请日：2011-11-18

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L21/823431

摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer; a first fin being formed by patterning the semiconductor layer; and a second fin being formed by patterning the semiconductor layer, wherein: top sides of the first and second fins have the same height; bottom sides of the first and second fins adjoin the semiconductor layer; and the second fin is higher than the first fin. According to the present disclosure, a plurality of semiconductor devices with different dimensions can be integrated on the same wafer. As a result, manufacturing process can be shortened and manufacturing cost can be reduced. Furthermore, devices with different driving capabilities can be provided.

摘要翻译： 本发明提供一种半导体器件及其制造方法。 半导体器件包括：半导体层; 通过图案化半导体层形成第一鳍片; 并且通过图案化半导体层形成第二鳍片，其中：第一鳍片和第二鳍片的顶侧具有相同的高度; 第一和第二散热片的底面邻接半导体层; 第二鳍高于第一鳍。 根据本公开，可以将多个具有不同尺寸的半导体器件集成在同一晶片上。 结果，可以缩短制造工序，降低制造成本。 此外，可以提供具有不同驱动能力的装置。

公开(公告)号：US09343602B2

公开(公告)日：2016-05-17

申请号：US13950510

申请日：2013-07-25

申请人： Zhijiong Luo ,  Huilong Zhu ,  Haizhou Yin

发明人： Zhijiong Luo ,  Huilong Zhu ,  Haizhou Yin

IPC分类号： H01L31/0352 ,  H01L31/04 ,  H01L31/042 ,  H01L31/05 ,  H01L31/18 ,  H01L31/20

CPC分类号： H01L31/035281 ,  H01L31/042 ,  H01L31/0504 ,  H01L31/1804 ,  H01L31/202 ,  Y02E10/50 ,  Y02E10/547 ,  Y02P70/521

摘要： The present invention provides a solar cell unit, which comprises a semiconductor plate of first-type doping or second-type doping; wherein the semiconductor plate has a first surface and a second surface opposite to the first surface; the semiconductor plate comprises a first-type doping region and second-type doping region, both the first-type doping region and the second-type doping region are located on the first surface of the semiconductor plate; a first sheet is provided on the side surface of the semiconductor plate that is adjacent to the first-type doping region, and a second sheet is provided on the side surface of the semiconductor plate that is adjacent to the second type doping region.

摘要翻译： 本发明提供一种太阳能电池单元，其包括第一种掺杂或二次掺杂的半导体板; 其中所述半导体板具有与所述第一表面相对的第一表面和第二表面; 所述半导体板包括第一类型掺杂区域和第二类型掺杂区域，所述第一类型掺杂区域和所述第二类型掺杂区域都位于所述半导体板件的所述第一表面上; 第一片设置在与第一型掺杂区相邻的半导体板的侧表面上，并且第二片设置在与第二类型掺杂区相邻的半导体板的侧表面上。

公开(公告)号：US09240351B2

公开(公告)日：2016-01-19

申请号：US13063731

申请日：2010-06-22

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L21/70 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/7845

摘要： The devices are manufactured by replacement gate process and replacement sidewall spacer process, and both tensile stress in the channel region of NMOS device and compressive stress in the channel region of PMOS device are increased by forming a first stress layer with compressive stress in the space within the first metal gate layer of NMOS and a second stress layer with tensile stress in the space within the second metal gate layer of PMOS, respectively. After formation of the stress layers, sidewall spacers of the gate stacks of PMOS and NMOS devices are removed so as to release stress in the channel regions. In particular, stress structure with opposite stress may be formed on sidewalls of the gate stacks of the NMOS device and PMOS device and on a portion of the source region and the drain region, in order to further increase both tensile stress of the NMOS device and compressive stress of the PMOS device.

摘要翻译： 器件通过更换栅极工艺和替换侧壁间隔工艺制造，NMOS器件的沟道区域中的拉伸应力和PMOS器件的沟道区域中的压应力均增加，在第一应力层内形成压缩应力 NMOS的第一金属栅极层和在PMOS的第二金属栅极层内的空间中具有拉伸应力的第二应力层。 在形成应力层之后，去除PMOS和NMOS器件的栅叠层的侧壁间隔物，以释放沟道区中的应力。 特别地，具有相反应力的应力结构可以形成在NMOS器件和PMOS器件的栅极堆叠的侧壁上，并且在源极区域和漏极区域的一部分上形成，以便进一步增加NMOS器件的拉伸应力和 PMOS器件的压应力。