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    Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices
    111.
    发明授权
    Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices 有权

    公开(公告)号：US11823972B2

    公开(公告)日：2023-11-21

    申请号：US16040746

    申请日：2018-07-20

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

    IPC: H01L23/367 ,  H01L25/065 ,  H01L23/498 ,  H01L23/373

    CPC classification number: H01L23/367 ,  H01L23/3737 ,  H01L23/49838 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06517

    Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device comprising at least one first thermally conductive structure proximate at least one of the first integrated circuit device, the second integrated circuit device, and the substrate; and a second thermally conductive structure disposed over the first thermally conductive structure(s), the first integrated circuit device, and the second integrated circuit device, wherein the first thermally conductive structure(s) have a lower electrical conductivity than an electrical conductivity of the second thermally conductive structure. The first thermally conductive structure(s) may be formed by an additive process or may be pre-formed and attached to at least one of the first integrated circuit device, the second integrated circuit device, and the substrate.

    Zero-misalignment two-via structures
    113.
    发明授权
    Zero-misalignment two-via structures 有权

    公开(公告)号：US11694951B2

    公开(公告)日：2023-07-04

    申请号：US17537406

    申请日：2021-11-29

    Applicant: Intel Corporation

    Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Brandon Rawlings ,  Johanna Swan

    IPC: H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538

    CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5386

    Abstract: A device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS is directly coupled to the interconnect. The ZM2VS may further include the dielectric on a conductive pad, a first via on a first seed, and the first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS may also have a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

    Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices
    114.
    发明授权
    Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices 有权

    公开(公告)号：US11621208B2

    公开(公告)日：2023-04-04

    申请号：US16040748

    申请日：2018-07-20

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

    IPC: H01L23/367 ,  H01L25/065 ,  H01L23/498

    Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device comprising at least one first thermally conductive structure proximate at least one of the first integrated circuit device, the second integrated circuit device, and the substrate; and a second thermally conductive structure disposed over the first thermally conductive structure(s), the first integrated circuit device, and the second integrated circuit device, wherein the first thermally conductive structure(s) have a lower electrical conductivity than an electrical conductivity of the second thermally conductive structure. The first thermally conductive structure(s) may be formed by an additive process or may be pre-formed and attached to at least one of the first integrated circuit device, the second integrated circuit device, and the substrate.

    Heat spreading layer integrated within a composite IC die structure and methods of forming the same
    115.
    发明授权
    Heat spreading layer integrated within a composite IC die structure and methods of forming the same 有权

    公开(公告)号：US11581238B2

    公开(公告)日：2023-02-14

    申请号：US17318887

    申请日：2021-05-12

    Applicant: Intel Corporation

    Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Jimin Yao ,  Veronica Strong

    IPC: H01L23/373 ,  H01L21/768 ,  H01L25/065 ,  H01L23/48

    Abstract: A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.

    LIQUID COOLED INTERPOSER FOR INTEGRATED CIRCUIT STACK
    117.
    发明申请
    LIQUID COOLED INTERPOSER FOR INTEGRATED CIRCUIT STACK 有权

    公开(公告)号：US20220399249A1

    公开(公告)日：2022-12-15

    申请号：US17346895

    申请日：2021-06-14

    Applicant: Intel Corporation

    Inventor： Georgios Dogiamis ,  Qiang Yu ,  Feras Eid ,  Adel Elsherbini ,  Kimin Jun ,  Johanna Swan ,  Shawna Liff

    IPC: H01L23/473 ,  H01L23/13 ,  H01L23/538 ,  H05K7/20 ,  H01L25/065

    Abstract: An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

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