公开(公告)号：US20070148863A1

公开(公告)日：2007-06-28

申请号：US11440864

申请日：2006-05-24

申请人： Dae-Young Seo ,  Ki-Ro Hong ,  Do-Hyung Kim

发明人： Dae-Young Seo ,  Ki-Ro Hong ,  Do-Hyung Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/10894 ,  H01L29/6653 ,  H01L29/6656

摘要： A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate lines over a substrate, wherein the substrate is defined into a cell region and a peripheral region, forming a gate spacer layer over the gate lines, the gate spacer layer including a buffer layer, an insulation layer, and a barrier layer, forming a mask pattern over the barrier layer in a manner to cover the cell region and open the peripheral region, performing an anisotropic etching method on the gate spacer layer using the mask pattern as an etch mask to form gate spacers on sidewalls of the gate lines in the peripheral region, performing an ion implantation process to form source/drain regions in the peripheral region, and simultaneously removing the mask pattern and the barrier layer.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成多个栅极线，其中将衬底限定为单元区域和外围区域，在栅极线上形成栅极间隔层，栅极间隔层包括缓冲层，绝缘层， 以及阻挡层，以覆盖单元区域的方式在阻挡层上形成掩模图案并打开外围区域，使用掩模图案作为蚀刻掩模在栅极间隔层上进行各向异性蚀刻方法，以形成栅极间隔物 在周边区域中的栅极线的侧壁，执行离子注入工艺以在周边区域中形成源极/漏极区域，并且同时去除掩模图案和阻挡层。

公开(公告)号：US20070120230A1

公开(公告)日：2007-05-31

申请号：US11585083

申请日：2006-10-24

申请人： Shin-Hye Kim ,  Ju-Bum Lee ,  Do-Hyung Kim

发明人： Shin-Hye Kim ,  Ju-Bum Lee ,  Do-Hyung Kim

IPC分类号： H01L21/8242 ,  H01L21/20 ,  H01L23/58 ,  H01L21/31

CPC分类号： H01L21/31625 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/31111 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

摘要： In a layer structure, a method of forming the layer structure, a method of manufacturing a capacitor having the layer structure and a method of manufacturing a semiconductor device having the capacitor, a structure may be formed on a substrate. A first insulation layer including at least one kind of impurities may be formed on the structure. A flatness of the first insulation layer may fluctuate according to the type and concentration of the impurities. The first insulation layer may include silicate glass doped with first impurities including an element in Group III and/or second impurities including an element in Group V. The flatness of the first insulation layer may improve in proportion to the concentration of the first impurities whereas in inverse proportion to the concentration of the second impurities. Accordingly, the flatness of the first insulation layer may be determined by adjusting the type and concentration of the impurities.

摘要翻译： 在层结构中，形成层结构的方法，制造具有层结构的电容器的方法以及制造具有电容器的半导体器件的方法可以在基板上形成。 可以在结构上形成包括至少一种杂质的第一绝缘层。 第一绝缘层的平坦度可能根据杂质的类型和浓度而波动。 第一绝缘层可以包括掺杂有包括第III族中的元素的第一杂质的硅酸盐玻璃和/或包含第V族中的元素的第二杂质。第一绝缘层的平坦度可以与第一杂质的浓度成比例地改善，而在 与第二杂质的浓度成反比。 因此，可以通过调整杂质的种类和浓度来确定第一绝缘层的平坦度。

公开(公告)号：US20050179840A1

公开(公告)日：2005-08-18

申请号：US11031938

申请日：2005-01-06

申请人： Won-Sang Park ,  Sang-Woo Kim ,  Jae-Young Lee ,  Sung-Eun Cha ,  Jae-Ik Lim ,  Jae-Hyun Kim ,  Do-Hyung Kim

发明人： Won-Sang Park ,  Sang-Woo Kim ,  Jae-Young Lee ,  Sung-Eun Cha ,  Jae-Ik Lim ,  Jae-Hyun Kim ,  Do-Hyung Kim

IPC分类号： G02B5/23 ,  G02F1/1335 ,  G02F1/136 ,  G02F1/1368 ,  H01L29/786

CPC分类号： G02F1/133514 ,  G02F1/133528 ,  G02F1/133555 ,  G02F2001/133565

摘要： A color filer panel includes a first substrate, a light reflecting member, a color filter, and a light polarizing layer. The light reflecting member is formed on the first substrate. The light reflecting member reflects at least a portion of an external light. The color filter is formed on the light reflecting member. The light polarizing layer is formed over the color filter. Advantageously the time for manufacturing the color filter panel is reduced. Furthermore, a misalignment between the first substrate and the light reflecting member or between the first substrate and the light polarizing layer, which occurs when the light reflecting member or the light polarizing layer is formed in a plate type, is reduced to enhance productivity. Additionally, the light before and after being reflected by the light reflecting member has substantially the same color to enhance display quality.

摘要翻译： 彩色滤光片面板包括第一基板，光反射部件，滤色器和光偏振层。 光反射部件形成在第一基板上。 光反射部件反射外部光的至少一部分。 滤光器形成在光反射部件上。 光偏振层形成在滤色器的上方。 有利地，减少了用于制造滤色器面板的时间。 此外，减少了当光反射部件或光偏振层形成为板状时发生的第一基板和光反射部件之间或第一基板和光偏振层之间的偏移，以提高生产率。 此外，由光反射构件反射的光之前和之后的光具有基本上相同的颜色以增强显示质量。

公开(公告)号：US06878597B2

公开(公告)日：2005-04-12

申请号：US10397970

申请日：2003-03-26

申请人： Do-Hyung Kim

发明人： Do-Hyung Kim

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/44 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6656

摘要： Methods of forming a source/drain region can include the steps of forming a gate electrode on a substrate and forming a lightly doped source/drain region in the substrate self-aligned to the gate electrode. A first spacer can be formed on a side wall of the gate electrode. A second spacer can be formed on the first spacer on the side wall separate from the first spacer to provide a multilayer spacer on the side wall. A heavily doped source/drain region can be formed in the substrate self-aligned to the multilayer spacer. Related structures are also disclosed.

摘要翻译： 形成源极/漏极区域的方法可以包括以下步骤：在衬底上形成栅电极，并在与栅电极自对准的衬底中形成轻掺杂的源/漏区。 可以在栅电极的侧壁上形成第一间隔物。 可以在与第一间隔物分开的侧壁上的第一间隔件上形成第二间隔件，以在侧壁上提供多层间隔物。 可以在与多层间隔物自对准的衬底中形成重掺杂源/漏区。 还公开了相关结构。

公开(公告)号：US06818489B2

公开(公告)日：2004-11-16

申请号：US10121205

申请日：2002-04-11

申请人： Do-Hyung Kim ,  Jin-Ho Kim ,  Byung-Jun Hwang

发明人： Do-Hyung Kim ,  Jin-Ho Kim ,  Byung-Jun Hwang

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/823425 ,  H01L29/6659

摘要： A semiconductor device having LDD-type source/drain regions and a method of fabricating the same are provided. The semiconductor device includes at least a pair of gate patterns disposed on a semiconductor substrate and LDD-type source/drain regions disposed at both sides of the gate patterns. The substrate having the gate patterns and the LDD-type source/drain regions is covered with a conformal etch stop layer. The etch stop layer is covered with an interlayer insulating layer. The LDD-type source/drain region is exposed by a contact hole that penetrates the interlayer insulating layer and the etch stop layer. The method of forming the LDD-type source/drain regions and the etch stop layer includes forming low-concentration source/drain regions at both sides of the gate patterns and forming the conformal etch stop layer on the substrate having the low-concentration source/drain regions. Gate spacers are then formed on the sidewalls of the gate patterns. Using the gate patterns and the gate spacers as implantation masks, impurity ions are implanted into the semiconductor substrate to form high-concentration source/drain regions. The spacers are then selectively removed. An interlayer insulating layer is formed on the substrate where the spacers are removed.

摘要翻译： 提供具有LDD型源极/漏极区域的半导体器件及其制造方法。 半导体器件包括设置在半导体衬底上的至少一对栅极图案和设置在栅极图案两侧的LDD型源极/漏极区域。 具有栅极图案和LDD型源极/漏极区域的衬底被保形蚀刻停止层覆盖。 蚀刻停止层被层间绝缘层覆盖。 LDD型源极/漏极区域通过穿透层间绝缘层和蚀刻停止层的接触孔露出。 形成LDD型源极/漏极区域和蚀刻停止层的方法包括在栅极图案的两侧形成低浓度源极/漏极区域，并在具有低浓度源/漏极区域的衬底上形成保形蚀刻停止层， 漏区。 然后在栅极图案的侧壁上形成栅极间隔物。 使用栅极图案和栅极间隔物作为注入掩模，将杂质离子注入到半导体衬底中以形成高浓度源极/漏极区域。 然后选择性地去除间隔物。 在基板上形成层间绝缘层，其中隔离物被去除。

公开(公告)号：US06610565B2

公开(公告)日：2003-08-26

申请号：US10017237

申请日：2001-12-14

申请人： Do-Hyung Kim ,  Jin-Ho Kim ,  Byung-Jun Hwang

发明人： Do-Hyung Kim ,  Jin-Ho Kim ,  Byung-Jun Hwang

IPC分类号： H01L2100

CPC分类号： H01L21/823814 ,  H01L21/823864

摘要： A method of forming a CMOS type semiconductor device comprises forming a gate electrode pattern on a surface of a substrate in NMOS and PMOS regions, forming spacers on side walls of the gate electrode pattern in the NMOS and PMOS regions, and doping n and p-type impurities heavily to the surface of the substrate in the NMOS and PMOS regions, respectively. After doping the p and n-type impurities heavily, the spacers are removed. The method further includes doping the n and p-type impurities lightly to the surface of the substrate in the NMOS and PMOS regions on which the spacers are removed. Alternatively, the light impurity implantation can be carried out before forming the spacers. Also, the light impurity implantation can be carried out to the surface of the substrate in one of the NMOS and PMOS regions before forming the spacers and to the surface of the substrate in the other of the NMOS and PMOS regions after removing the spacers.

公开(公告)号：US06372672B1

公开(公告)日：2002-04-16

申请号：US09478064

申请日：2000-01-05

申请人： Do-Hyung Kim ,  Ju-Bum Lee ,  Byung-Keun Hwang

发明人： Do-Hyung Kim ,  Ju-Bum Lee ,  Byung-Keun Hwang

IPC分类号： H01L2131

CPC分类号： H01L21/3185 ,  C23C16/345 ,  H01L21/0332

摘要： A method of forming a silicon nitride layer in a semiconductor device manufacturing process. The silicon nitride layer (SixNyHz) is formed by PE-CVD technique at low temperature to have at most 0.35 hydrogen composition. The resulting silicon nitride layer has substantially no Si—H bonding as compared with a silicon nitride layer formed at high temperature, thereby reducing thermal stress variation during annealing. The resulting silicon nitride layer exhibits reduced thermal stress variation before and after deposition, preventing a popping phenomenon and reducing the stress applied to the underlying layer.

摘要翻译： 一种在半导体器件制造工艺中形成氮化硅层的方法。 氮化硅层（SixNyHz）通过PE-CVD技术在低温下形成，具有至多0.35个氢组成。 与在高温下形成的氮化硅层相比，所得到的氮化硅层基本上不具有Si-H键，从而降低退火时的热应力变化。 所得到的氮化硅层在沉积之前和之后表现出降低的热应力变化，防止弹出现象并降低施加到下层的应力。

公开(公告)号：US08705779B2

公开(公告)日：2014-04-22

申请号：US12458028

申请日：2009-06-29

申请人： Kang Eun Lee ,  Do-Hyung Kim ,  Chang Yong Son

发明人： Kang Eun Lee ,  Do-Hyung Kim ,  Chang Yong Son

IPC分类号： H04R5/033

CPC分类号： H04S3/00

摘要： A surround sound virtualization apparatus and method. The surround sound virtualization apparatus may include an audio decoder to perform head-related transfer function (HRTF) filtering, and a time delay unit to provide a time delay to a plurality of output signals of the audio decoder.

摘要翻译： 环绕声虚拟化设备和方法。 环绕声虚拟化装置可以包括用于执行头相关传送功能（HRTF）滤波的音频解码器，以及为音频解码器的多个输出信号提供时间延迟的时间延迟单元。

公开(公告)号：US08456212B2

公开(公告)日：2013-06-04

申请号：US13050652

申请日：2011-03-17

申请人： Woo-Seok Kim ,  Do-Hyung Kim ,  Tae-Kwang Jang ,  Se-Hyung Jeon

发明人： Woo-Seok Kim ,  Do-Hyung Kim ,  Tae-Kwang Jang ,  Se-Hyung Jeon

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty correcting circuit includes a duty steerer circuit, a differential clock generator, and a charge pump circuit. The duty steerer circuit corrects a duty cycle of an input clock signal in response to a duty control signal and generates an output clock signal. The differential clock generator generates two internal clock signals having a phase difference of 180° from each other based on the output clock signal. The charge pump circuit performs a charge pump operation in a differential mode in response to the internal clock signals to generate a duty control signal.

摘要翻译： 一个占空比校正电路包括占空比转子电路，差分时钟发生器和电荷泵电路。 占空比电路响应于占空比控制信号校正输入时钟信号的占空比，并产生输出时钟信号。 差分时钟发生器基于输出时钟信号产生彼此相位差为180°的两个内部时钟信号。 电荷泵电路响应于内部时钟信号在差分模式下执行电荷泵操作以产生占空比控制信号。

公开(公告)号：US08395569B2

公开(公告)日：2013-03-12

申请号：US12588257

申请日：2009-10-08

申请人： Kyung-Hee Min ,  Sung-Joon Bae ,  Joon-Suk Lee ,  Do-Hyung Kim

发明人： Kyung-Hee Min ,  Sung-Joon Bae ,  Joon-Suk Lee ,  Do-Hyung Kim

IPC分类号： G09G3/32

CPC分类号： H01L27/3246 ,  H01L27/3253

摘要： The present invention relates to an organic electroluminescent display (OELD) device, more particularly, to a dual panel type OELD device and a method of fabricating the same. The OLED structure has first and second barrier walls having a reverse-taper shape with respect to the first substrate and first and second side surfaces, wherein the walls define novel polymer patterns with varying heights relative to each other.

摘要翻译： 本发明涉及一种有机电致发光显示器（OELD）器件，更具体地涉及一种双面板型OELD器件及其制造方法。 OLED结构具有相对于第一基板和第一和第二侧表面具有倒锥形的第一和第二阻挡壁，其中壁限定相对于彼此具有不同高度的新型聚合物图案。