公开(公告)号：US20110111586A1

公开(公告)日：2011-05-12

申请号：US13004162

申请日：2011-01-11

申请人： Luigi Colombo ,  Mark R. Visokay ,  James J. Chambers

发明人： Luigi Colombo ,  Mark R. Visokay ,  James J. Chambers

IPC分类号： H01L21/3205

CPC分类号： H01L21/823835 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/28176 ,  H01L21/28518 ,  H01L21/76819 ,  H01L21/823842

摘要： A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction.

摘要翻译： 一种设置完全硅化半导体器件的功能的方法及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅极堆叠包括电介质层，介电层上的硅化物层，其限定金属 - 电介质层界面，以及硅化物上的多晶硅层 层），在栅极堆叠上沉积金属层，退火以引起多晶硅层和金属层之间的反应，以及通过反应将功函数赋予掺杂剂输送到金属 - 电介质层界面。

公开(公告)号：US20110091647A1

公开(公告)日：2011-04-21

申请号：US12774342

申请日：2010-05-05

申请人： Luigi Colombo ,  Xuesong Li ,  Rodney S. Ruoff

发明人： Luigi Colombo ,  Xuesong Li ,  Rodney S. Ruoff

IPC分类号： C23C16/44 ,  C23C16/26

CPC分类号： C23C16/26 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/186

摘要： Processes for synthesizing graphene films. Graphene films may be synthesized by heating a metal or a dielectric on a substrate to a temperature between 400° C. and 1,400° C. The metal or dielectric is exposed to an organic compound thereby growing graphene from the organic compound on the metal or dielectric. The metal or dielectric is later cooled to room temperature. As a result of the above process, standalone graphene films may be synthesized with properties equivalent to exfoliated graphene from natural graphite that is scalable to size far greater than that available on silicon carbide, single crystal silicon substrates or from natural graphite.

摘要翻译： 合成石墨烯薄膜的方法。 石墨烯膜可以通过将基板上的金属或电介质加热到400℃和1400℃之间的温度来合成。将金属或电介质暴露于有机化合物，从而从金属或电介质上的有机化合物生长石墨烯 。 然后将金属或电介质冷却至室温。 作为上述方法的结果，独立的石墨烯膜可以合成具有相当于天然石墨剥离的石墨烯的性质，该石墨烯的尺寸远大于在碳化硅，单晶硅衬底或天然石墨上可获得的尺寸。

公开(公告)号：US20100224851A1

公开(公告)日：2010-09-09

申请号：US12706116

申请日：2010-02-16

申请人： Luigi Colombo ,  Robert M. Wallace ,  Rodney S. Ruoff

发明人： Luigi Colombo ,  Robert M. Wallace ,  Rodney S. Ruoff

IPC分类号： H01L29/15 ,  C04B35/536 ,  H01L21/20

CPC分类号： H01L21/02612 ,  H01L21/02527

摘要： A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.

摘要翻译： 一种使用碳的离子注入合成石墨烯的方法和半导体器件。 使用离子注入将碳注入金属中。 在碳分布在金属中之后，对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。 然后将金属/石墨烯表面转移到电介质层，使得石墨烯层被放置在电介质层的顶部上。 然后去除金属层。 或者，将凹陷区域图案化并蚀刻在位于基底上的电介质层中。 金属后来形成在这些凹陷区域。 然后使用离子注入将碳注入到金属中。 然后可以对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。

公开(公告)号：US20090298749A1

公开(公告)日：2009-12-03

申请号：US12476785

申请日：2009-06-02

申请人： Martin Stogniew ,  Luigi Colombo ,  Romeo Clabatti

发明人： Martin Stogniew ,  Luigi Colombo ,  Romeo Clabatti

IPC分类号： A61K38/14 ,  A61P31/04

CPC分类号： C07H7/033 ,  A61K31/704 ,  A61K38/00 ,  C07H13/06 ,  C07H15/203 ,  C07K9/008 ,  Y02A50/475 ,  Y02A50/478 ,  Y02A50/479 ,  Y02A50/481 ,  A61K2300/00

摘要： The invention provides methods and compositions for treatment of bacterial infections. The composition may be a combination of factors, which include A0, A1, B1, B2, C0, C1, isoB0, and MAG, in the presence of low level solvent. Methods of the invention include administration of dalbavancin formulations for treatment of a bacterial infection, in particular a Gram-positive bacterial infection of skin and soft tissue. Dosing regimens include multiple dose administration of dalbavancin, which often remains at therapeutic levels in the bloodstream for at least one week, providing prolonged therapeutic action against a bacterial infection. Dosing regimens for renal patients are also included.

摘要翻译： 本发明提供了用于治疗细菌感染的方法和组合物。 该组合物可以是低浓度溶剂存在下的A0，A1，B1，B2，C0，C1，isoBO和MAG等因素的组合。 本发明的方法包括施用达巴万星制剂用于治疗细菌感染，特别是皮肤和软组织的革兰氏阳性细菌感染。 给药方案包括达巴万星的多剂量给药，其通常在血流中保持治疗水平至少一周，为细菌感染提供长时间的治疗作用。 还包括肾脏患者的给药方案。

公开(公告)号：US07601578B2

公开(公告)日：2009-10-13

申请号：US11924132

申请日：2007-10-25

申请人： Luigi Colombo ,  James J. Chambers ,  Mark R. Visokay ,  Antonio Luis Pacheco Rotondaro

发明人： Luigi Colombo ,  James J. Chambers ,  Mark R. Visokay ,  Antonio Luis Pacheco Rotondaro

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/02318 ,  C23C16/56 ,  H01L21/02323 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/318 ,  H01L29/518 ,  H01L29/78

摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.

摘要翻译： 一种改善高卡门电介质膜（104）性能的方法。 对高卡帕膜（104）进行两步退火处理。 第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。 第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。

公开(公告)号：US07601577B2

公开(公告)日：2009-10-13

申请号：US11870631

申请日：2007-10-11

申请人： James Joseph Chambers ,  Mark Robert Visokay ,  Luigi Colombo ,  Antonio Luis Pacheco Rotondaro

发明人： James Joseph Chambers ,  Mark Robert Visokay ,  Luigi Colombo ,  Antonio Luis Pacheco Rotondaro

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/823842

摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

摘要翻译： 公开了具有不同功函数的金属栅极晶体管。 在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。 在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。

公开(公告)号：US20090104745A1

公开(公告)日：2009-04-23

申请号：US11877124

申请日：2007-10-23

申请人： Hyesook Hong ,  Luigi Colombo ,  Jinhan Choi

发明人： Hyesook Hong ,  Luigi Colombo ,  Jinhan Choi

IPC分类号： H01L21/336

CPC分类号： H01L21/28123 ,  H01L21/823842

摘要： In accordance with the present teachings, methods of making dual doped polysilicon gates are provided. The method can include providing a semiconductor structure including a plurality of polysilicon gates having a first critical dimension disposed over a dielectric layer and planarizing the plurality of polysilicon gates with a spin-on material to form a plurality of planarized polysilicon gates. The method can further include doping an exposed first region with p-type dopants to form a plurality of p-doped planarized polysilicon gates and doping an exposed second region with n-type dopants to form a plurality of n-doped planarized polysilicon gates. The method can also include removing the spin-on material to form a plurality of p-doped polysilicon gates and a plurality of n-doped polysilicon gates, wherein critical dimension of each of the plurality of n-doped polysilicon gates and the plurality of p-doped polysilicon gates are substantially similar to the first critical dimension.

摘要翻译： 根据本教导，提供制造双掺杂多晶硅栅极的方法。 该方法可以包括提供包括多个多晶硅栅极的半导体结构，该多晶硅栅极具有设置在电介质层上的第一临界尺寸，并且用旋涂材料平坦化多个多晶硅栅极以形成多个平坦化的多晶硅栅极。 该方法还可以包括用p型掺杂剂掺杂暴露的第一区域以形成多个p掺杂的平坦化多晶硅栅极，并用n型掺杂剂掺杂暴露的第二区域以形成多个n掺杂的平坦化多晶硅栅极。 该方法还可以包括去除旋涂材料以形成多个p掺杂多晶硅栅极和多个n掺杂多晶硅栅极，其中多个n掺杂多晶硅栅极和多个p掺杂多晶硅栅极中的每一个的临界尺寸 掺杂的多晶硅栅极基本上类似于第一临界尺寸。

公开(公告)号：US07351632B2

公开(公告)日：2008-04-01

申请号：US11118842

申请日：2005-04-29

申请人： Mark Robert Visokay ,  Luigi Colombo ,  James Joseph Chambers

发明人： Mark Robert Visokay ,  Luigi Colombo ,  James Joseph Chambers

IPC分类号： H01L21/8238

CPC分类号： H01L27/105 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/11 ,  H01L27/1116

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An oxide layer is formed in core and I/O regions of a semiconductor device (506). The oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A silicon nitride layer is grown (516) within PMOS regions of the core and I/O regions by a low temperature thermal process. Subsequently, an oxidation process is performed (518) that oxidizes the silicon nitride into silicon oxynitride.

摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成氧化物层。 氧化物层从器件的核心区域移除（508）。 在芯和I / O区域上形成高k电介质层（510）。 然后，从芯和I / O区域的PMOS区域去除高k电介质层（512）。 通过低温热处理在核心和I / O区域的PMOS区域内生长氮化硅层（516）。 随后，进行氧化处理（518），其将氮化硅氧化成氮氧化硅。

公开(公告)号：US07321154B2

公开(公告)日：2008-01-22

申请号：US11465219

申请日：2006-08-17

申请人： Luigi Colombo ,  James J Chambers ,  Mark R Visokay

发明人： Luigi Colombo ,  James J Chambers ,  Mark R Visokay

IPC分类号： H01L29/76

CPC分类号： H01L21/823842 ,  H01L29/4958

摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

公开(公告)号：US07291890B2

公开(公告)日：2007-11-06

申请号：US11339393

申请日：2006-01-25

申请人： Mark R. Visokay ,  Antonio L. P. Rotondaro ,  Luigi Colombo

发明人： Mark R. Visokay ,  Antonio L. P. Rotondaro ,  Luigi Colombo

IPC分类号： H01L29/76

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.

摘要翻译： 具有高k栅极电介质层和硅或金属栅极的MOSFET结构，与等离子体或离子注入一起对高k栅极介电层进行非晶化处理。