公开(公告)号：US10783940B2

公开(公告)日：2020-09-22

申请号：US16799599

申请日：2020-02-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  H03K5/156

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

公开(公告)号：US10593383B1

公开(公告)日：2020-03-17

申请号：US16121217

申请日：2018-09-04

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim

IPC: G06F12/00 ,  G11C7/22 ,  G06F1/12 ,  G06F13/16

Abstract: Methods, systems, and devices for system-level timing budget are described. Each memory die in a memory device may determine an offset between its system clock signal and its data clock signal. The offsets of each memory die in the memory device may be different; e.g., having different magnitudes and/or polarities. A memory die in the memory device may adjust its own data clock signal by a delay that is based on the offsets of two or more memory die in the device. The memory die may adjust its data clock signal by setting a fuse in a delay adjuster on the memory die. Adjusting the data clock signal may match an offset of a first memory die with an offset of a second memory die.

公开(公告)号：US10467158B2

公开(公告)日：2019-11-05

申请号：US16035452

申请日：2018-07-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G11C7/22 ,  G06F13/16 ,  G06F9/30

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US20190267056A1

公开(公告)日：2019-08-29

申请号：US16274992

申请日：2019-02-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  John D. Porter

IPC: G11C7/22 ,  H03K5/156 ,  G11C11/4076 ,  G11C8/18

Abstract: Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode.

公开(公告)号：US10373660B1

公开(公告)日：2019-08-06

申请号：US16274992

申请日：2019-02-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  John D. Porter

IPC: G11C8/16 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  H03K5/156

Abstract: Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode.

公开(公告)号：US20190163653A1

公开(公告)日：2019-05-30

申请号：US16035452

申请日：2018-07-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30

CPC classification number: G06F13/1689 ,  G06F9/30145 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US20190163652A1

公开(公告)日：2019-05-30

申请号：US16035414

申请日：2018-07-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US10249354B1

公开(公告)日：2019-04-02

申请号：US15903934

申请日：2018-02-23

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  John D. Porter

IPC: G11C8/18 ,  G11C7/22 ,  G11C11/4076 ,  H03K5/156

Abstract: Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode.

公开(公告)号：US20190080743A1

公开(公告)日：2019-03-14

申请号：US16190504

申请日：2018-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  John D. Porter

IPC: G11C11/4076 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4091

Abstract: Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.

公开(公告)号：US20180247683A1

公开(公告)日：2018-08-30

申请号：US15445935

申请日：2017-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G11C7/22 ,  G11C8/10 ,  G11C8/18

CPC classification number: G11C7/222 ,  G11C7/109 ,  G11C11/4076 ,  G11C2207/2272

Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.